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ROM
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EEPROM
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Common
SFRs
Features Configuration Bits RAM map SFR map
PIC12CE673
CONFIG (address:0x2007, mask:0x3FFF, default:0x3FFF)
FOSC -- Oscillator selection bits (bitmask:0x0007)
FOSC = LP 0x3FF8 LP oscillator.
FOSC = XT 0x3FF9 XT oscillator.
FOSC = HS 0x3FFA HS oscillator.
FOSC = INTRCIO 0x3FFC INTRC, OSC2 is I/O.
FOSC = INTRCCLK 0x3FFD INTRC, Clockout on OSC2.
FOSC = EXTRCIO 0x3FFE EXTRC, OSC2 is I/O.
FOSC = EXTRCCLK 0x3FFF EXTRC, Clockout on OSC2.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF 0x3FF7 WDT disabled.
WDTE = ON 0x3FFF WDT enabled.
PWRTE -- Power Up Timer (bitmask:0x0010)
PWRTE = ON 0x3FEF Enabled.
PWRTE = OFF 0x3FFF Disabled.
MCLRE -- Master Clear Enable (bitmask:0x0080)
MCLRE = OFF 0x3F7F Master Clear disabled.
MCLRE = ON 0x3FFF Master Clear enabled.
CP -- Code Protection bits (bitmask:0x3F60)
CP = ALL 0x009F All memory is code protected.
CP = 75 0x15BF 0200h-03FEh code protected.
CP = 50 0x2ADF Do not use.
CP = OFF 0x3FFF code protection off.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.