| PIC12F1572 | ||||
|---|---|---|---|---|
| CONFIG1 (address:0x8007, mask:0x0EFB, default:0x0EFB) | ||||
| FOSC (bitmask:0x0003) | ||||
| FOSC = INTOSC | 0x3FFC | INTOSC oscillator; I/O function on CLKIN pin. | ||
| FOSC = ECL | 0x3FFD | ECL, External Clock, Low Power Mode (0-0.5 MHz); device clock supplied to CLKIN pin. | ||
| FOSC = ECM | 0x3FFE | ECM, External Clock, Medium Power Mode (0.5-4 MHz); device clock supplied to CLKIN pin. | ||
| FOSC = ECH | 0x3FFF | ECH, External Clock, High Power Mode (4-32 MHz); device clock supplied to CLKIN pin. | ||
| WDTE -- Watchdog Timer Enable (bitmask:0x0018) | ||||
| WDTE = OFF | 0x3FE7 | WDT disabled. | ||
| WDTE = SWDTEN | 0x3FEF | WDT controlled by the SWDTEN bit in the WDTCON register. | ||
| WDTE = NSLEEP | 0x3FF7 | WDT enabled while running and disabled in Sleep. | ||
| WDTE = ON | 0x3FFF | WDT enabled. | ||
| PWRTE -- Power-up Timer Enable (bitmask:0x0020) | ||||
| PWRTE = ON | 0x3FDF | PWRT enabled. | ||
| PWRTE = OFF | 0x3FFF | PWRT disabled. | ||
| MCLRE -- MCLR Pin Function Select (bitmask:0x0040) | ||||
| MCLRE = OFF | 0x3FBF | MCLR/VPP pin function is digital input. | ||
| MCLRE = ON | 0x3FFF | MCLR/VPP pin function is MCLR. | ||
| CP -- Flash Program Memory Code Protection (bitmask:0x0080) | ||||
| CP = ON | 0x3F7F | Program memory code protection is enabled. | ||
| CP = OFF | 0x3FFF | Program memory code protection is disabled. | ||
| BOREN -- Brown-out Reset Enable (bitmask:0x0600) | ||||
| BOREN = OFF | 0x39FF | Brown-out Reset disabled. | ||
| BOREN = SBODEN | 0x3BFF | Brown-out Reset controlled by the SBOREN bit in the BORCON register. | ||
| BOREN = NSLEEP | 0x3DFF | Brown-out Reset enabled while running and disabled in Sleep. | ||
| BOREN = ON | 0x3FFF | Brown-out Reset enabled. | ||
| CLKOUTEN -- Clock Out Enable (bitmask:0x0800) | ||||
| CLKOUTEN = ON | 0x37FF | CLKOUT function is enabled on the CLKOUT pin. | ||
| CLKOUTEN = OFF | 0x3FFF | CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin. | ||
| CONFIG2 (address:0x8008, mask:0x3F03, default:0x3F03) | ||||
| WRT -- Flash Memory Self-Write Protection (bitmask:0x0003) | ||||
| WRT = ALL | 0x3FFC | 000h to 7FFh write protected, no addresses may be modified by EECON control. | ||
| WRT = HALF | 0x3FFD | 000h to 3FFh write protected, 400h to 7FFh may be modified by EECON control. | ||
| WRT = BOOT | 0x3FFE | 000h to 1FFh write protected, 200h to 7FFh may be modified by EECON control. | ||
| WRT = OFF | 0x3FFF | Write protection off. | ||
| PLLEN -- PLL Enable (bitmask:0x0100) | ||||
| PLLEN = OFF | 0x3EFF | 4x PLL disabled. | ||
| PLLEN = ON | 0x3FFF | 4x PLL enabled. | ||
| STVREN -- Stack Overflow/Underflow Reset Enable (bitmask:0x0200) | ||||
| STVREN = OFF | 0x3DFF | Stack Overflow or Underflow will not cause a Reset. | ||
| STVREN = ON | 0x3FFF | Stack Overflow or Underflow will cause a Reset. | ||
| BORV -- Brown-out Reset Voltage Selection (bitmask:0x0400) | ||||
| BORV = HI | 0x3BFF | Brown-out Reset Voltage (Vbor), high trip point selected. | ||
| BORV = LO | 0x3FFF | Brown-out Reset Voltage (Vbor), low trip point selected. | ||
| LPBOREN -- Low Power Brown-out Reset enable bit (bitmask:0x0800) | ||||
| LPBOREN = ON | 0x37FF | LPBOR is enabled. | ||
| LPBOREN = OFF | 0x3FFF | LPBOR is disabled. | ||
| DEBUG -- Debugger enable bit (bitmask:0x1000) | ||||
| DEBUG = ON | 0x2FFF | Background debugger enabled. | ||
| DEBUG = OFF | 0x3FFF | Background debugger disabled. | ||
| LVP -- Low-Voltage Programming Enable (bitmask:0x2000) | ||||
| LVP = OFF | 0x1FFF | High-voltage on MCLR/VPP must be used for programming. | ||
| LVP = ON | 0x3FFF | Low-voltage programming enabled. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.