All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
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ROM
size
EEPROM
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Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16C505
CONFIG (address:0x0FFF, mask:0x0FFF, default:0x0FFF)
OSC -- Oscillator selection bits (bitmask:0x0007)
OSC = LP 0x0FF8 LP oscillator.
OSC = XT 0x0FF9 XT oscillator.
OSC = HS 0x0FFA HS oscillator.
OSC = IntRC_RB4EN 0x0FFC Internal RC No Clock.
OSC = IntRC_CLKOUTEN 0x0FFD Internal RC Clockout.
OSC = ExtRC_RB4EN 0x0FFE External RC No Clock.
OSC = ExtRC_CLKOUTEN 0x0FFF External RC Clockout.
WDT -- Watchdog timer enable bit (bitmask:0x0008)
WDT = OFF 0x0FF7 WDT disabled.
WDT = ON 0x0FFF WDT enabled.
MCLRE -- Master Clear Enable (bitmask:0x0020)
MCLRE = OFF 0x0FDF RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD.
MCLRE = ON 0x0FFF RB3/MCLR pin function is MCLR.
CP -- Code protection bit (bitmask:0x0FD0)
CP = ON 0x002F Code protection on.
CP = OFF 0x0FFF Code protection off.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.