All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16F18855
CONFIG1 (address:0x8007, mask:0x2977, default:0x2977)
FEXTOSC -- External Oscillator mode selection bits (bitmask:0x0007)
FEXTOSC = LP 0x3FF8 LP (crystal oscillator) optimized for 32.768kHz; PFM set to low power.
FEXTOSC = XT 0x3FF9 XT (crystal oscillator) above 500kHz, below 4MHz; PFM set to medium power.
FEXTOSC = HS 0x3FFA HS (crystal oscillator) above 4MHz; PFM set to high power.
FEXTOSC = Reserved 0x3FFB Reserved.
FEXTOSC = OFF 0x3FFC Oscillator not enabled.
FEXTOSC = ECL 0x3FFD EC below 500kHz; PFM set to low power.
FEXTOSC = ECM 0x3FFE EC for 500kHz to 8MHz; PFM set to medium power.
FEXTOSC = ECH 0x3FFF EC above 8MHz; PFM set to high power.
RSTOSC -- Power-up default value for COSC bits (bitmask:0x0070)
RSTOSC = HFINT32 0x3F8F HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1.
RSTOSC = HFINTPLL 0x3F9F HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1 (FOSC = 32 MHz).
RSTOSC = EXT4X 0x3FAF EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = Reserved 0x3FBF Reserved.
RSTOSC = SOSC 0x3FCF SOSC.
RSTOSC = LFINT 0x3FDF LFINTOSC.
RSTOSC = HFINT1 0x3FEF HFINTOSC (1MHz).
RSTOSC = EXT1X 0x3FFF EXTOSC operating per FEXTOSC bits.
CLKOUTEN -- Clock Out Enable bit (bitmask:0x0100)
CLKOUTEN = ON 0x3EFF CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
CLKOUTEN = OFF 0x3FFF CLKOUT function is disabled; i/o or oscillator function on OSC2.
CSWEN -- Clock Switch Enable bit (bitmask:0x0800)
CSWEN = OFF 0x37FF The NOSC and NDIV bits cannot be changed by user software.
CSWEN = ON 0x3FFF Writing to NOSC and NDIV is allowed.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x2000)
FCMEN = OFF 0x1FFF FSCM timer disabled.
FCMEN = ON 0x3FFF FSCM timer enabled.
CONFIG2 (address:0x8008, mask:0x3EE3, default:0x3EE3)
MCLRE -- Master Clear Enable bit (bitmask:0x0001)
MCLRE = OFF 0x3FFE MCLR pin function is port defined function.
MCLRE = ON 0x3FFF MCLR pin is Master Clear function.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0002)
PWRTE = ON 0x3FFD PWRT enabled.
PWRTE = OFF 0x3FFF PWRT disabled.
LPBOREN -- Low-Power BOR enable bit (bitmask:0x0020)
LPBOREN = ON 0x3FDF ULPBOR enabled.
LPBOREN = OFF 0x3FFF ULPBOR disabled.
BOREN -- Brown-out reset enable bits (bitmask:0x00C0)
BOREN = OFF 0x3F3F Brown-out reset disabled.
BOREN = SBOREN 0x3F7F Brown-out reset enabled according to SBOREN bit.
BOREN = NSLEEP 0x3FBF Brown-out Reset enabled while running, disabled in sleep; SBOREN is ignored.
BOREN = ON 0x3FFF Brown-out Reset Enabled, SBOREN bit is ignored.
BORV -- Brown-out Reset Voltage Selection (bitmask:0x0200)
BORV = HI 0x3DFF Brown-out Reset Voltage (VBOR) is set to 2.7V.
BORV = LO 0x3FFF Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices.
ZCD -- Zero-cross detect disable (bitmask:0x0400)
ZCD = ON 0x3BFF Zero-cross detect circuit is always enabled.
ZCD = OFF 0x3FFF Zero-cross detect circuit is disabled at POR.
PPS1WAY -- Peripheral Pin Select one-way control (bitmask:0x0800)
PPS1WAY = OFF 0x37FF The PPSLOCK bit can be set and cleared repeatedly by software.
PPS1WAY = ON 0x3FFF The PPSLOCK bit can be cleared and set only once in software.
STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x1000)
STVREN = OFF 0x2FFF Stack Overflow or Underflow will not cause a reset.
STVREN = ON 0x3FFF Stack Overflow or Underflow will cause a reset.
DEBUG -- Background Debugger (bitmask:0x2000)
DEBUG = ON 0x1FFF background debugger enabled.
DEBUG = OFF 0x3FFF Background Debugger disabled.
CONFIG3 (address:0x8009, mask:0x3F7F, default:0x3F7F)
WDTCPS -- WDT Period Select bits (bitmask:0x001F)
WDTCPS = WDTCPS_0 0x3FE0 Divider ratio 1:32.
WDTCPS = WDTCPS_1 0x3FE1 Divider ratio 1:64.
WDTCPS = WDTCPS_2 0x3FE2 Divider ratio 1:128.
WDTCPS = WDTCPS_3 0x3FE3 Divider ratio 1:256.
WDTCPS = WDTCPS_4 0x3FE4 Divider ratio 1:512.
WDTCPS = WDTCPS_5 0x3FE5 Divider ratio 1:1024.
WDTCPS = WDTCPS_6 0x3FE6 Divider ratio 1:2048.
WDTCPS = WDTCPS_7 0x3FE7 Divider ratio 1:4096.
WDTCPS = WDTCPS_8 0x3FE8 Divider ratio 1:8192.
WDTCPS = WDTCPS_9 0x3FE9 Divider ratio 1:16384.
WDTCPS = WDTCPS_10 0x3FEA Divider ratio 1:32768.
WDTCPS = WDTCPS_11 0x3FEB Divider ratio 1:65536.
WDTCPS = WDTCPS_12 0x3FEC Divider ratio 1:131072.
WDTCPS = WDTCPS_13 0x3FED Divider ratio 1:262144.
WDTCPS = WDTCPS_14 0x3FEE Divider ratio 1:524299.
WDTCPS = WDTCPS_15 0x3FEF Divider ratio 1:1048576.
WDTCPS = WDTCPS_16 0x3FF0 Divider ratio 1:2097152.
WDTCPS = WDTCPS_17 0x3FF1 Divider ratio 1:4194304.
WDTCPS = WDTCPS_18 0x3FF2 Divider ratio 1:8388608.
WDTCPS = WDTCPS_19 0x3FF3 Divider ratio 1:32.
WDTCPS = WDTCPS_20 0x3FF4 Divider ratio 1:32.
WDTCPS = WDTCPS_21 0x3FF5 Divider ratio 1:32.
WDTCPS = WDTCPS_22 0x3FF6 Divider ratio 1:32.
WDTCPS = WDTCPS_23 0x3FF7 Divider ratio 1:32.
WDTCPS = WDTCPS_24 0x3FF8 Divider ratio 1:32.
WDTCPS = WDTCPS_25 0x3FF9 Divider ratio 1:32.
WDTCPS = WDTCPS_26 0x3FFA Divider ratio 1:32.
WDTCPS = WDTCPS_27 0x3FFB Divider ratio 1:32.
WDTCPS = WDTCPS_28 0x3FFC Divider ratio 1:32.
WDTCPS = WDTCPS_29 0x3FFD Divider ratio 1:32.
WDTCPS = WDTCPS_30 0x3FFE Divider ratio 1:32.
WDTCPS = WDTCPS_31 0x3FFF Divider ratio 1:65536; software control of WDTPS.
WDTE -- WDT operating mode (bitmask:0x0060)
WDTE = OFF 0x3F9F WDT Disabled, SWDTEN is ignored.
WDTE = SWDTEN 0x3FBF WDT enabled/disabled by SWDTEN bit in WDTCON0.
WDTE = NSLEEP 0x3FDF WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored.
WDTE = ON 0x3FFF WDT enabled regardless of sleep; SWDTEN ignored.
WDTCWS -- WDT Window Select bits (bitmask:0x0700)
WDTCWS = WDTCWS_0 0x38FF window delay = 87.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_1 0x39FF window delay = 75 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_2 0x3AFF window delay = 62.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_3 0x3BFF window delay = 50 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_4 0x3CFF window delay = 37.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_5 0x3DFF window delay = 25 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_6 0x3EFF window always open (100%); no software control; keyed access required.
WDTCWS = WDTCWS_7 0x3FFF window always open (100%); software control; keyed access not required.
WDTCCS -- WDT input clock selector (bitmask:0x3800)
WDTCCS = LFINTOSC 0x07FF WDT reference clock is the 31.0kHz LFINTOSC output.
WDTCCS = HFINTOSC 0x0FFF WDT reference clock is the 31.25 kHz HFINTOSC.
WDTCCS = SC 0x3FFF Software Control.
CONFIG4 (address:0x800A, mask:0x3003, default:0x3003)
WRT -- UserNVM self-write protection bits (bitmask:0x0003)
WRT = ON 0x3FFC 0x0000 to 0x1FFF write protected.
WRT = WRT_lower 0x3FFD 0x0000 to x0FFF write protected.
WRT = WRT_upper 0x3FFE 0x0000 to 0x01FF write protected.
WRT = OFF 0x3FFF Write protection off.
SCANE -- Scanner Enable bit (bitmask:0x1000)
SCANE = not_available 0x2FFF Scanner module is not available for use.
SCANE = available 0x3FFF Scanner module is available for use.
LVP -- Low Voltage Programming Enable bit (bitmask:0x2000)
LVP = OFF 0x1FFF High Voltage on MCLR/Vpp must be used for programming.
LVP = ON 0x3FFF Low Voltage programming enabled. MCLR/Vpp pin function is MCLR.
CONFIG5 (address:0x800B, mask:0x0003, default:0x0003)
CP -- UserNVM Program memory code protection bit (bitmask:0x0001)
CP = ON 0x3FFE Program Memory code protection enabled.
CP = OFF 0x3FFF Program Memory code protection disabled.
CPD -- DataNVM code protection bit (bitmask:0x0002)
CPD = ON 0x3FFD Data EEPROM code protection enabled.
CPD = OFF 0x3FFF Data EEPROM code protection disabled.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:47 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.