All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16F506
CONFIG (address:0x0FFF, mask:0x007F, default:0x007F)
OSC -- Oscillator Selection bits (bitmask:0x0007)
OSC = LP 0x0FF8 LP oscillator and 18 ms DRT.
OSC = XT 0x0FF9 XT oscillator and 18 ms DRT.
OSC = HS 0x0FFA HS oscillator and 18 ms DRT.
OSC = EC 0x0FFB EC Osc With RB4 and 1.125 ms DRT.
OSC = IntRC_RB4EN 0x0FFC INTRC With RB4 and 1.125 ms DRT.
OSC = IntRC_CLKOUTEN 0x0FFD INTRC With CLKOUT and 1.125 ms DRT.
OSC = ExtRC_RB4EN 0x0FFE EXTRC With RB4 and 1.125 ms DRT.
OSC = ExtRC_CLKOUTEN 0x0FFF EXTRC With CLKOUT and 1.125 ms DRT.
WDT -- Watchdog Timer Enable bit (bitmask:0x0008)
WDT = OFF 0x0FF7 WDT disabled.
WDT = ON 0x0FFF WDT enabled.
CP -- Code Protect (bitmask:0x0010)
CP = ON 0x0FEF Code protection on.
CP = OFF 0x0FFF Code protection off.
MCLRE -- Master Clear Enable bit (bitmask:0x0020)
MCLRE = OFF 0x0FDF RB3/MCLR pin functions as RB3, MCLR tied internally to VDD.
MCLRE = ON 0x0FFF RB3/MCLR pin functions as MCLR.
IOSCFS -- Internal Oscillator Frequency Select bit (bitmask:0x0040)
IOSCFS = OFF 0x0FBF 4 MHz INTOSC Speed.
IOSCFS = ON 0x0FFF 8 MHz INTOSC Speed.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.