| PIC16F526 | ||||
|---|---|---|---|---|
| CONFIG (address:0x0FFF, mask:0x00FF, default:0x00FF) | ||||
| FOSC -- Oscillator (bitmask:0x0007) | ||||
| FOSC = LP | 0x0FF8 | LP oscillator and 18 ms DRT. | ||
| FOSC = XT | 0x0FF9 | XT oscillator and 18 ms DRT. | ||
| FOSC = HS | 0x0FFA | HS oscillator and 18 ms DRT. | ||
| FOSC = EC | 0x0FFB | EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT. | ||
| FOSC = INTRC_RB4 | 0x0FFC | INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT. | ||
| FOSC = INTRC_CLKOUT | 0x0FFD | INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT. | ||
| FOSC = ExtRC_RB4 | 0x0FFE | EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT. | ||
| FOSC = ExtRC_CLKOUT | 0x0FFF | EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT. | ||
| WDTE -- Watchdog Timer Enable bit (bitmask:0x0008) | ||||
| WDTE = OFF | 0x0FF7 | Disabled. | ||
| WDTE = ON | 0x0FFF | Enabled. | ||
| CP -- Code Protection bit (bitmask:0x0010) | ||||
| CP = ON | 0x0FEF | Code protection on. | ||
| CP = OFF | 0x0FFF | Code protection off. | ||
| MCLRE -- Master Clear Enable bit (bitmask:0x0020) | ||||
| MCLRE = OFF | 0x0FDF | RB3/MCLR functions as RB3, MCLR internally tied to Vdd. | ||
| MCLRE = ON | 0x0FFF | RB3/MCLR functions as MCLR. | ||
| IOSCFS -- Internal Oscillator Frequency Select (bitmask:0x0040) | ||||
| IOSCFS = 4MHz | 0x0FBF | 4 MHz INTOSC Speed. | ||
| IOSCFS = 8MHz | 0x0FFF | 8 MHz INTOSC Speed. | ||
| CPDF -- Code Protection bit - Flash Data Memory (bitmask:0x0080) | ||||
| CPDF = ON | 0x0F7F | Code protection on. | ||
| CPDF = OFF | 0x0FFF | Code protection off. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.