| PIC16F720 | ||||
|---|---|---|---|---|
| CONFIG1 (address:0x2007, mask:0x137B, default:0x137B) | ||||
| FOSC -- Oscillator Selection bits (bitmask:0x0003) | ||||
| FOSC = INTOSCIO | 0x3FFC | INTOSCIO oscillator: I/O function on RA4/CLKO pin, I/O function on RA5/CLKI. | ||
| FOSC = INTOSCCLK | 0x3FFD | INTOSC oscillator: CLKO function on RA4/CLKO pin, I/O function on RA5/CLKI. | ||
| FOSC = ECIO | 0x3FFE | EC oscillator: I/O function on RA4/CLKO pin, CLKI on RA5/CLKI. | ||
| FOSC = ECCLK | 0x3FFF | EC oscillator: CLKO function on RA4/CLKO pin, CLKI on RA5/CLKI. | ||
| WDTE -- Watchdog Timer Enable bit (bitmask:0x0008) | ||||
| WDTE = OFF | 0x3FF7 | WDT disabled. | ||
| WDTE = ON | 0x3FFF | WDT enabled. | ||
| PWRTE -- Power-up Timer Enable bit (bitmask:0x0010) | ||||
| PWRTE = ON | 0x3FEF | PWRT enabled. | ||
| PWRTE = OFF | 0x3FFF | PWRT disabled. | ||
| MCLRE -- RA3/MCLR/VPP Pin Function Select bit (bitmask:0x0020) | ||||
| MCLRE = OFF | 0x3FDF | RA3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled. | ||
| MCLRE = ON | 0x3FFF | RA3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. | ||
| CP -- Flash Program Memory Code Protection bit (bitmask:0x0040) | ||||
| CP = ON | 0x3FBF | 0000h to 07FFh code protection on. | ||
| CP = OFF | 0x3FFF | Code protection off. | ||
| BOREN -- Brown-out Reset Enable bits (bitmask:0x0300) | ||||
| BOREN = OFF | 0x3CFF | Brown-out Reset disabled (Preconditioned State). | ||
| BOREN = NSLEEP | 0x3EFF | Brown-out Reset enabled during operation and disabled in Sleep. | ||
| BOREN = ON | 0x3FFF | Brown-out Reset enabled. | ||
| PLLEN -- INTOSC PLLEN Enable Bit (bitmask:0x1000) | ||||
| PLLEN = OFF | 0x2FFF | INTOSC Frequency is 500 kHz. | ||
| PLLEN = ON | 0x3FFF | INTOSC Frequency is 16 MHz (32x). | ||
| CONFIG2 (address:0x2008, mask:0x0003, default:0x0003) | ||||
| WRTEN -- Flash memory self-write protection bits (bitmask:0x0003) | ||||
| WRTEN = FULL | 0x3FFC | 0h to FFFh of flash memory write protected, no address may be modified. | ||
| WRTEN = HALF | 0x3FFD | 0h to 7FFh of flash memory write protected, 800h to FFFh may be modified. | ||
| WRTEN = BOOT | 0x3FFE | 0h to 1FFh of flash memory write protected, 200h to FFFh may be modified. | ||
| WRTEN = OFF | 0x3FFF | Write protection off. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.