| PIC16F737 | ||||
|---|---|---|---|---|
| CONFIG1 (address:0x2007, mask:0x39FF, default:0x39FF) | ||||
| WDTE -- Watchdog Timer Enable bit (bitmask:0x0004) | ||||
| WDTE = OFF | 0x3FFB | WDT disabled. | ||
| WDTE = ON | 0x3FFF | WDT enabled. | ||
| PWRTE -- Power-up Timer Enable bit (bitmask:0x0008) | ||||
| PWRTE = ON | 0x3FF7 | PWRT enabled. | ||
| PWRTE = OFF | 0x3FFF | PWRT disabled. | ||
| FOSC -- Oscillator Selection bits (bitmask:0x0013) | ||||
| FOSC = LP | 0x3FEC | LP oscillator. | ||
| FOSC = XT | 0x3FED | XT oscillator. | ||
| FOSC = HS | 0x3FEE | HS oscillator. | ||
| FOSC = EC | 0x3FEF | EXTCLK; port I/O function on OSC2/CLKO/RA6. | ||
| FOSC = INTOSCIO | 0x3FFC | INTRC oscillator; port I/O function on OSC1/CLKI/RA7 and OSC2/CLKO/RA6. | ||
| FOSC = INTOSCCLK | 0x3FFD | INTRC oscillator; CLKO function on OSC2/CLKO/RA6 and port I/O function on OSC1/CLKI/RA7. | ||
| FOSC = EXTRCIO | 0x3FFE | EXTRC oscillator; port I/O function on OSC2/CLKO/RA6. | ||
| FOSC = EXTRCCLK | 0x3FFF | EXTRC oscillator; CLKO function on OSC2/CLKO/RA6. | ||
| MCLRE -- MCLR/VPP/RE3 Pin Function Select bit (bitmask:0x0020) | ||||
| MCLRE = OFF | 0x3FDF | MCLR/VPP/RE3 pin function is digital input only, MCLR gated to '1'. | ||
| MCLRE = ON | 0x3FFF | MCLR/VPP/RE3 pin function is MCLR. | ||
| BOREN -- Brown-out Reset Enable bit (bitmask:0x0040) | ||||
| BOREN = OFF | 0x3FBF | Disabled. | ||
| BOREN = ON | 0x3FFF | Enabled. | ||
| BORV -- Brown-out Reset Voltage bits (bitmask:0x0180) | ||||
| BORV = 45 | 0x3E7F | VBOR set to 4.5V. | ||
| BORV = 42 | 0x3EFF | VBOR set to 4.2V. | ||
| BORV = 27 | 0x3F7F | VBOR set to 2.7V. | ||
| BORV = 20 | 0x3FFF | VBOR set to 2.0V. | ||
| DEBUG -- In-Circuit Debugger Mode bit (bitmask:0x0800) | ||||
| DEBUG = ON | 0x37FF | In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger. | ||
| DEBUG = OFF | 0x3FFF | In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins. | ||
| CCP2MX -- CCP2 Multiplex bit (bitmask:0x1000) | ||||
| CCP2MX = RB3 | 0x2FFF | CCP2 is on RB3. | ||
| CCP2MX = RC1 | 0x3FFF | CCP2 is on RC1. | ||
| CP -- Flash Program Memory Code Protection bits (bitmask:0x2000) | ||||
| CP = ON | 0x1FFF | 0000h to 0FFFh code-protected. | ||
| CP = OFF | 0x3FFF | Code protection off. | ||
| CONFIG2 (address:0x2008, mask:0x0043, default:0x0043) | ||||
| FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x0001) | ||||
| FCMEN = OFF | 0x3FFE | Fail-Safe Clock Monitor disabled. | ||
| FCMEN = ON | 0x3FFF | Fail-Safe Clock Monitor enabled. | ||
| IESO -- Internal External Switchover bit (bitmask:0x0002) | ||||
| IESO = OFF | 0x3FFD | Internal External Switchover mode disabled. | ||
| IESO = ON | 0x3FFF | Internal External Switchover mode enabled. | ||
| BORSEN -- Brown-out Reset Software Enable bit (bitmask:0x0040) | ||||
| BORSEN = OFF | 0x3FBF | Disabled. | ||
| BORSEN = ON | 0x3FFF | Enabled. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.