All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16F887
CONFIG1 (address:0x2007, mask:0x3FFF, default:0x3FFF)
FOSC -- Oscillator Selection bits (bitmask:0x0007)
FOSC = LP 0x3FF8 LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = XT 0x3FF9 XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = HS 0x3FFA HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = EC 0x3FFB EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN.
FOSC = INTRC_NOCLKOUT 0x3FFC INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
FOSC = INTRC_CLKOUT 0x3FFD INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
FOSC = EXTRC_NOCLKOUT 0x3FFE RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN.
FOSC = EXTRC_CLKOUT 0x3FFF RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF 0x3FF7 WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
WDTE = ON 0x3FFF WDT enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0010)
PWRTE = ON 0x3FEF PWRT enabled.
PWRTE = OFF 0x3FFF PWRT disabled.
MCLRE -- RE3/MCLR pin function select bit (bitmask:0x0020)
MCLRE = OFF 0x3FDF RE3/MCLR pin function is digital input, MCLR internally tied to VDD.
MCLRE = ON 0x3FFF RE3/MCLR pin function is MCLR.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON 0x3FBF Program memory code protection is enabled.
CP = OFF 0x3FFF Program memory code protection is disabled.
CPD -- Data Code Protection bit (bitmask:0x0080)
CPD = ON 0x3F7F Data memory code protection is enabled.
CPD = OFF 0x3FFF Data memory code protection is disabled.
BOREN -- Brown Out Reset Selection bits (bitmask:0x0300)
BOREN = OFF 0x3CFF BOR disabled.
BOREN = SBODEN 0x3DFF BOR controlled by SBOREN bit of the PCON register.
BOREN = NSLEEP 0x3EFF BOR enabled during operation and disabled in Sleep.
BOREN = ON 0x3FFF BOR enabled.
IESO -- Internal External Switchover bit (bitmask:0x0400)
IESO = OFF 0x3BFF Internal/External Switchover mode is disabled.
IESO = ON 0x3FFF Internal/External Switchover mode is enabled.
FCMEN -- Fail-Safe Clock Monitor Enabled bit (bitmask:0x0800)
FCMEN = OFF 0x37FF Fail-Safe Clock Monitor is disabled.
FCMEN = ON 0x3FFF Fail-Safe Clock Monitor is enabled.
LVP -- Low Voltage Programming Enable bit (bitmask:0x1000)
LVP = OFF 0x2FFF RB3 pin has digital I/O, HV on MCLR must be used for programming.
LVP = ON 0x3FFF RB3/PGM pin has PGM function, low voltage programming enabled.
DEBUG -- In-Circuit Debugger Mode bit (bitmask:0x2000)
DEBUG = ON 0x1FFF In_Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger.
DEBUG = OFF 0x3FFF In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins.
CONFIG2 (address:0x2008, mask:0x0700, default:0x0700)
BOR4V -- Brown-out Reset Selection bit (bitmask:0x0100)
BOR4V = BOR21V 0x3EFF Brown-out Reset set to 2.1V.
BOR4V = BOR40V 0x3FFF Brown-out Reset set to 4.0V.
WRT -- Flash Program Memory Self Write Enable bits (bitmask:0x0600)
WRT = HALF 0x39FF 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
WRT = 1FOURTH 0x3BFF 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control.
WRT = 256 0x3DFF 0000h to 00FFh write protected, 0100h to 1FFFh may be modified by EECON control.
WRT = OFF 0x3FFF Write protection off.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.