All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16LF1618
CONFIG1 (address:0x8007, mask:0x0EE3, default:0x0EE3)
FOSC (bitmask:0x0003)
FOSC = INTOSC 0x3FFC INTOSC oscillator: I/O function on CLKIN pin.
FOSC = ECL 0x3FFD ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
FOSC = ECM 0x3FFE ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
FOSC = ECH 0x3FFF ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
PWRTE -- Power-up Timer Enable (bitmask:0x0020)
PWRTE = ON 0x3FDF PWRT enabled.
PWRTE = OFF 0x3FFF PWRT disabled.
MCLRE -- MCLR Pin Function Select (bitmask:0x0040)
MCLRE = OFF 0x3FBF MCLR/VPP pin function is digital input.
MCLRE = ON 0x3FFF MCLR/VPP pin function is MCLR.
CP -- Flash Program Memory Code Protection (bitmask:0x0080)
CP = ON 0x3F7F Program memory code protection is enabled.
CP = OFF 0x3FFF Program memory code protection is disabled.
BOREN -- Brown-out Reset Enable (bitmask:0x0600)
BOREN = OFF 0x39FF Brown-out Reset disabled.
BOREN = SBODEN 0x3BFF Brown-out Reset controlled by the SBOREN bit in the BORCON register.
BOREN = NSLEEP 0x3DFF Brown-out Reset enabled while running and disabled in Sleep.
BOREN = ON 0x3FFF Brown-out Reset enabled.
CLKOUTEN -- Clock Out Enable (bitmask:0x0800)
CLKOUTEN = ON 0x37FF CLKOUT function is enabled on the CLKOUT pin.
CLKOUTEN = OFF 0x3FFF CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
CONFIG2 (address:0x8008, mask:0x3F87, default:0x3F87)
WRT -- Flash Memory Self-Write Protection (bitmask:0x0003)
WRT = ALL 0x3FFC 000h to 1FFFh write protected, no addresses may be modified by PMCON control.
WRT = HALF 0x3FFD 000h to FFFh write protected, 1000h to 1FFFh may be modified by PMCON control.
WRT = BOOT 0x3FFE 000h to 1FFh write protected, 200h to 1FFFh may be modified by PMCON control.
WRT = OFF 0x3FFF Write protection off.
PPS1WAY -- Peripheral Pin Select one-way control (bitmask:0x0004)
PPS1WAY = OFF 0x3FFB The PPSLOCK bit can be set and cleared repeatedly by software.
PPS1WAY = ON 0x3FFF The PPSLOCK bit cannot be cleared once it is set by software.
ZCD -- Zero Cross Detect Disable Bit (bitmask:0x0080)
ZCD = ON 0x3F7F ZCD always enabled.
ZCD = OFF 0x3FFF ZCD disable. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON.
PLLEN -- PLL Enable Bit (bitmask:0x0100)
PLLEN = OFF 0x3EFF 4x PLL is enabled when software sets the SPLLEN bit.
PLLEN = ON 0x3FFF 4x PLL is always enabled.
STVREN -- Stack Overflow/Underflow Reset Enable (bitmask:0x0200)
STVREN = OFF 0x3DFF Stack Overflow or Underflow will not cause a Reset.
STVREN = ON 0x3FFF Stack Overflow or Underflow will cause a Reset.
BORV -- Brown-out Reset Voltage Selection (bitmask:0x0400)
BORV = HI 0x3BFF Brown-out Reset Voltage (Vbor), high trip point selected.
BORV = LO 0x3FFF Brown-out Reset Voltage (Vbor), low trip point selected.
LPBOR -- Low-Power Brown Out Reset (bitmask:0x0800)
LPBOR = ON 0x37FF Low-Power BOR is enabled.
LPBOR = OFF 0x3FFF Low-Power BOR is disabled.
DEBUG -- Debugger enable bit (bitmask:0x1000)
DEBUG = ON 0x2FFF Background debugger enabled.
DEBUG = OFF 0x3FFF Background debugger disabled.
LVP -- Low-Voltage Programming Enable (bitmask:0x2000)
LVP = OFF 0x1FFF High-voltage on MCLR/VPP must be used for programming.
LVP = ON 0x3FFF Low-voltage programming enabled.
CONFIG3 (address:0x8009, mask:0x3F7F, default:0x3F7F)
WDTCPS -- WDT Period Select (bitmask:0x001F)
WDTCPS = WDTCPS0 0x3FE0 1:32 (1 ms period).
WDTCPS = WDTCPS1 0x3FE1 1:64 (2 ms period).
WDTCPS = WDTCPS2 0x3FE2 1:128 (4 ms period).
WDTCPS = WDTCPS3 0x3FE3 1:256 (8 ms period).
WDTCPS = WDTCPS4 0x3FE4 1:512 (16 ms period).
WDTCPS = WDTCPS5 0x3FE5 1:1024 (32 ms period).
WDTCPS = WDTCPS6 0x3FE6 1:2048 (64 ms period).
WDTCPS = WDTCPS7 0x3FE7 1:4096 (128 ms period).
WDTCPS = WDTCPS8 0x3FE8 1:8192 (256 ms period).
WDTCPS = WDTCPS9 0x3FE9 1:16384 (512 ms period).
WDTCPS = WDTCPSA 0x3FEA 1:32768 (1 s period).
WDTCPS = WDTCPSB 0x3FEB 1:65536 (2 s period).
WDTCPS = WDTCPSC 0x3FEC 1:131072 (4 s period).
WDTCPS = WDTCPSD 0x3FED 1:262144 (8 s period).
WDTCPS = WDTCPSE 0x3FEE 1:524299 (16 s period).
WDTCPS = WDTCPSF 0x3FEF 1:1048576 (32 s period).
WDTCPS = WDTCPS10 0x3FF0 1:2097152 (64 s period).
WDTCPS = WDTCPS11 0x3FF1 1:4194304 (128 s period).
WDTCPS = WDTCPS12 0x3FF2 1:8388608 (256 s period).
WDTCPS = WDTCPS1F 0x3FFF Software Control (WDTPS).
WDTE -- Watchdog Timer Enable (bitmask:0x0060)
WDTE = OFF 0x3F9F WDT disabled.
WDTE = SWDTEN 0x3FBF WDT controlled by the SWDTEN bit in the WDTCON register.
WDTE = NSLEEP 0x3FDF WDT enabled while running and disabled in Sleep.
WDTE = ON 0x3FFF WDT enabled.
WDTCWS -- WDT Window Select (bitmask:0x0700)
WDTCWS = WDTCWS125 0x38FF 12.5 percent window open time.
WDTCWS = WDTCWS25 0x39FF 25 percent window open time.
WDTCWS = WDTCWS375 0x3AFF 37.5 percent window open time.
WDTCWS = WDTCWS50 0x3BFF 50 percent window open time.
WDTCWS = WDTCWS625 0x3CFF 62.5 percent window open time.
WDTCWS = WDTCWS75 0x3DFF 75 percent window open time.
WDTCWS = WDTCWS100 0x3EFF 100 percent window open time (Legacy WDT) .
WDTCWS = WDTCWSSW 0x3FFF Software WDT window size control (WDTWS bits).
WDTCCS -- WDT Input Clock Selector (bitmask:0x3800)
WDTCCS = LFINTOSC 0x07FF 31.0kHz LFINTOSC.
WDTCCS = MFINTOSC 0x0FFF 31.25 kHz HFINTOSC (MFINTOSC).
WDTCCS = SWC 0x3FFF Software control, controlled by WDTCS bits.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:48 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.