All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC16LF18323
CONFIG1 (address:0x8007, mask:0x2977, default:0x2977)
FEXTOSC -- FEXTOSC External Oscillator mode Selection bits (bitmask:0x0007)
FEXTOSC = LP 0x3FF8 LP (crystal oscillator) optimized for 32.768 kHz.
FEXTOSC = XT 0x3FF9 XT (crystal oscillator) from 100 kHz to 4 MHz.
FEXTOSC = HS 0x3FFA HS (crystal oscillator) above 4 MHz.
FEXTOSC = OFF 0x3FFC Oscillator not enabled.
FEXTOSC = ECL 0x3FFD EC (external clock) below 100 kHz.
FEXTOSC = ECM 0x3FFE EC (external clock) for 100 kHz to 8 MHz.
FEXTOSC = ECH 0x3FFF EC (external clock) above 8 MHz.
RSTOSC -- Power-up default value for COSC bits (bitmask:0x0070)
RSTOSC = HFINT32 0x3F8F HFINTOSC with 2x PLL (32MHz).
RSTOSC = EXT4X 0x3F9F EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = SOSC 0x3FBF SOSC (31kHz).
RSTOSC = LFINT 0x3FCF LFINTOSC (31kHz).
RSTOSC = HFINT1 0x3FEF HFINTOSC (1MHz).
RSTOSC = EXT1X 0x3FFF EXTOSC operating per FEXTOSC bits.
CLKOUTEN -- Clock Out Enable bit (bitmask:0x0100)
CLKOUTEN = ON 0x3EFF CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
CLKOUTEN = OFF 0x3FFF CLKOUT function is disabled; I/O or oscillator function on OSC2.
CSWEN -- Clock Switch Enable bit (bitmask:0x0800)
CSWEN = OFF 0x37FF The NOSC and NDIV bits cannot be changed by user software.
CSWEN = ON 0x3FFF Writing to NOSC and NDIV is allowed.
FCMEN -- Fail-Safe Clock Monitor Enable (bitmask:0x2000)
FCMEN = OFF 0x1FFF Fail-Safe Clock Monitor is disabled.
FCMEN = ON 0x3FFF Fail-Safe Clock Monitor is enabled.
CONFIG2 (address:0x8008, mask:0x3AEF, default:0x3AEF)
MCLRE -- Master Clear Enable bit (bitmask:0x0001)
MCLRE = OFF 0x3FFE MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
MCLRE = ON 0x3FFF MCLR/VPP pin function is MCLR; Weak pull-up enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0002)
PWRTE = ON 0x3FFD PWRT enabled.
PWRTE = OFF 0x3FFF PWRT disabled.
WDTE -- Watchdog Timer Enable bits (bitmask:0x000C)
WDTE = OFF 0x3FF3 WDT disabled; SWDTEN is ignored.
WDTE = SWDTEN 0x3FF7 WDT controlled by the SWDTEN bit in the WDTCON register.
WDTE = SLEEP 0x3FFB WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
WDTE = ON 0x3FFF WDT enabled, SWDTEN is ignored.
LPBOREN -- Low-power BOR enable bit (bitmask:0x0020)
LPBOREN = ON 0x3FDF ULPBOR enabled.
LPBOREN = OFF 0x3FFF ULPBOR disabled.
BOREN -- Brown-out Reset Enable bits (bitmask:0x00C0)
BOREN = OFF 0x3F3F Brown-out Reset disabled.
BOREN = SBOREN 0x3F7F Brown-out Reset enabled according to SBOREN.
BOREN = SLEEP 0x3FBF Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
BOREN = ON 0x3FFF Brown-out Reset enabled, SBOREN bit ignored.
BORV -- Brown-out Reset Voltage selection bit (bitmask:0x0200)
BORV = HIGH 0x3DFF Brown-out voltage (Vbor) set to 2.7V.
BORV = LOW 0x3FFF Brown-out voltage (Vbor) set to 2.45V.
PPS1WAY -- PPSLOCK bit One-Way Set Enable bit (bitmask:0x0800)
PPS1WAY = OFF 0x37FF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
PPS1WAY = ON 0x3FFF The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x1000)
STVREN = OFF 0x2FFF Stack Overflow or Underflow will not cause a Reset.
STVREN = ON 0x3FFF Stack Overflow or Underflow will cause a Reset.
DEBUG -- Debugger enable bit (bitmask:0x2000)
DEBUG = ON 0x1FFF Background debugger enabled.
DEBUG = OFF 0x3FFF Background debugger disabled.
CONFIG3 (address:0x8009, mask:0x2003, default:0x2003)
WRT -- User NVM self-write protection bits (bitmask:0x0003)
WRT = ALL 0x3FFC 0000h to 07FFh write protected, no addresses may be modified.
WRT = HALF 0x3FFD 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
WRT = BOOT 0x3FFE 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
WRT = OFF 0x3FFF Write protection off.
LVP -- Low Voltage Programming Enable bit (bitmask:0x2000)
LVP = OFF 0x1FFF High Voltage on MCLR/VPP must be used for programming.
LVP = ON 0x3FFF Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
CONFIG4 (address:0x800A, mask:0x0003, default:0x0003)
CP -- User NVM Program Memory Code Protection bit (bitmask:0x0001)
CP = ON 0x3FFE User NVM code protection enabled.
CP = OFF 0x3FFF User NVM code protection disabled.
CPD -- Data NVM Memory Code Protection bit (bitmask:0x0002)
CPD = ON 0x3FFD Data NVM code protection enabled.
CPD = OFF 0x3FFF Data NVM code protection disabled.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:49 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.