| PIC16LF88 | ||||
|---|---|---|---|---|
| CONFIG1 (address:0x2007, mask:0x3FFF, default:0x3FFF) | ||||
| WDTE -- Watchdog Timer Enable bit (bitmask:0x0004) | ||||
| WDTE = OFF | 0x3FFB | WDT disabled. | ||
| WDTE = ON | 0x3FFF | WDT enabled. | ||
| PWRTE -- Power-up Timer Enable bit (bitmask:0x0008) | ||||
| PWRTE = ON | 0x3FF7 | PWRT enabled. | ||
| PWRTE = OFF | 0x3FFF | PWRT disabled. | ||
| FOSC -- Oscillator Selection bits (bitmask:0x0013) | ||||
| FOSC = LP | 0x3FEC | LP oscillator. | ||
| FOSC = XT | 0x3FED | XT oscillator. | ||
| FOSC = HS | 0x3FEE | HS oscillator. | ||
| FOSC = EC | 0x3FEF | ECIO; port I/O function on RA6/OSC2/CLKO. | ||
| FOSC = INTOSCIO | 0x3FFC | INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin. | ||
| FOSC = INTOSCCLK | 0x3FFD | INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin. | ||
| FOSC = EXTRCIO | 0x3FFE | EXTRC oscillator; port I/O function on RA6/OSC2/CLKO. | ||
| FOSC = EXTRCCLK | 0x3FFF | EXTRC oscillator; CLKO function on RA6/OSC2/CLKO. | ||
| MCLRE -- RA5/MCLR/VPP Pin Function Select bit (bitmask:0x0020) | ||||
| MCLRE = OFF | 0x3FDF | RA5/MCLR/VPP pin function is digital I/O, MCLR internally tied to VDD. | ||
| MCLRE = ON | 0x3FFF | RA5/MCLR/VPP pin function is MCLR. | ||
| BOREN -- Brown-out Reset Enable bit (bitmask:0x0040) | ||||
| BOREN = OFF | 0x3FBF | BOR disabled. | ||
| BOREN = ON | 0x3FFF | BOR enabled. | ||
| LVP -- Low-Voltage Programming Enable bit (bitmask:0x0080) | ||||
| LVP = OFF | 0x3F7F | RB3 is digital I/O, HV on MCLR must be used for programming. | ||
| LVP = ON | 0x3FFF | RB3/PGM pin has PGM function, Low-Voltage Programming enabled. | ||
| CPD -- Data EE Memory Code Protection bit (bitmask:0x0100) | ||||
| CPD = ON | 0x3EFF | Data EE memory code-protected. | ||
| CPD = OFF | 0x3FFF | Code protection off. | ||
| WRT -- Flash Program Memory Write Enable bits (bitmask:0x0600) | ||||
| WRT = ALL | 0x39FF | 0000h to 0FFFh write-protected. | ||
| WRT = 2048 | 0x3BFF | 0000h to 07FFh write-protected, 0800h to 0FFFh may be modified by EECON control. | ||
| WRT = 256 | 0x3DFF | 0000h to 00FFh write-protected, 0100h to 0FFFh may be modified by EECON control. | ||
| WRT = OFF | 0x3FFF | Write protection off. | ||
| DEBUG -- In-Circuit Debugger Mode bit (bitmask:0x0800) | ||||
| DEBUG = ON | 0x37FF | In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger. | ||
| DEBUG = OFF | 0x3FFF | In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins. | ||
| CCPMX -- CCP1 Pin Selection bit (bitmask:0x1000) | ||||
| CCPMX = RB3 | 0x2FFF | CCP1 function on RB3. | ||
| CCPMX = RB0 | 0x3FFF | CCP1 function on RB0. | ||
| CP -- Flash Program Memory Code Protection bit (bitmask:0x2000) | ||||
| CP = ON | 0x1FFF | 0000h to 0FFFh code-protected (all protected). | ||
| CP = OFF | 0x3FFF | Code protection off. | ||
| CONFIG2 (address:0x2008, mask:0x0003, default:0x0003) | ||||
| FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x0001) | ||||
| FCMEN = OFF | 0x3FFE | Fail-Safe Clock Monitor disabled. | ||
| FCMEN = ON | 0x3FFF | Fail-Safe Clock Monitor enabled. | ||
| IESO -- Internal External Switchover bit (bitmask:0x0002) | ||||
| IESO = OFF | 0x3FFD | Internal External Switchover mode disabled. | ||
| IESO = ON | 0x3FFF | Internal External Switchover mode enabled. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:47 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.