All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18F25K40
CONFIG1L (address:0x300000, mask:0x77, default:0x77)
FEXTOSC -- External Oscillator mode Selection bits (bitmask:0x07)
FEXTOSC = LP 0xF8 LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power.
FEXTOSC = XT 0xF9 XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power.
FEXTOSC = HS 0xFA HS (crystal oscillator) above 8 MHz; PFM set to high power.
FEXTOSC = RESERVED 0xFB Reserved (DO NOT USE).
FEXTOSC = OFF 0xFC Oscillator not enabled.
FEXTOSC = ECL 0xFD EC (external clock) below 100 kHz; PFM set to low power.
FEXTOSC = ECM 0xFE EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power.
FEXTOSC = ECH 0xFF EC (external clock) above 8 MHz; PFM set to high power.
RSTOSC -- Power-up default value for COSC bits (bitmask:0x70)
RSTOSC = HFINTOSC_64MHZ 0x8F HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1.
RSTOSC = RESERVED_1 0x9F Reserved.
RSTOSC = EXTOSC_4PLL 0xAF EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = RESERVED_2 0xBF Reserved.
RSTOSC = SOSC 0xCF Secondary Oscillator.
RSTOSC = LFINTOSC 0xDF Low-Frequency Oscillator.
RSTOSC = HFINTOSC_1MHZ 0xEF HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1.
RSTOSC = EXTOSC 0xFF EXTOSC operating per FEXTOSC bits (device manufacturing default).
CONFIG1H (address:0x300001, mask:0x29, default:0x29)
CLKOUTEN -- Clock Out Enable bit (bitmask:0x01)
CLKOUTEN = ON 0xFE CLKOUT function is enabled.
CLKOUTEN = OFF 0xFF CLKOUT function is disabled.
CSWEN -- Clock Switch Enable bit (bitmask:0x08)
CSWEN = OFF 0xF7 The NOSC and NDIV bits cannot be changed by user software.
CSWEN = ON 0xFF Writing to NOSC and NDIV is allowed.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x20)
FCMEN = OFF 0xDF Fail-Safe Clock Monitor disabled.
FCMEN = ON 0xFF Fail-Safe Clock Monitor enabled.
CONFIG2L (address:0x300002, mask:0xE3, default:0xE3)
MCLRE -- Master Clear Enable bit (bitmask:0x01)
MCLRE = INTMCLR 0xFE If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCLR.
MCLRE = EXTMCLR 0xFF If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR .
PWRTE -- Power-up Timer Enable bit (bitmask:0x02)
PWRTE = ON 0xFD Power up timer enabled.
PWRTE = OFF 0xFF Power up timer disabled.
LPBOREN -- Low-power BOR enable bit (bitmask:0x20)
LPBOREN = ON 0xDF ULPBOR enabled.
LPBOREN = OFF 0xFF ULPBOR disabled.
BOREN -- Brown-out Reset Enable bits (bitmask:0xC0)
BOREN = OFF 0x3F Brown-out Reset disabled.
BOREN = ON 0x7F Brown-out Reset enabled according to SBOREN.
BOREN = NOSLP 0xBF Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
BOREN = SBORDIS 0xFF Brown-out Reset enabled , SBOREN bit is ignored.
CONFIG2H (address:0x300003, mask:0xBF, default:0xBF)
BORV -- Brown Out Reset Voltage selection bits (bitmask:0x03)
BORV = VBOR_285 0xFC Brown-out Reset Voltage (VBOR) set to 2.85V.
BORV = VBOR_270 0xFD Brown-out Reset Voltage (VBOR) set to 2.70V.
BORV = VBOR_245 0xFE Brown-out Reset Voltage (VBOR) set to 2.45V.
BORV = VBOR_2P45 0xFF Brown-out Reset Voltage (VBOR) set to 2.45V.
ZCD -- ZCD Disable bit (bitmask:0x04)
ZCD = ON 0xFB ZCD always enabled.
ZCD = OFF 0xFF ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON.
PPS1WAY -- PPSLOCK bit One-Way Set Enable bit (bitmask:0x08)
PPS1WAY = OFF 0xF7 PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
PPS1WAY = ON 0xFF PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
STVREN -- Stack Full/Underflow Reset Enable bit (bitmask:0x10)
STVREN = OFF 0xEF Stack full/underflow will not cause Reset.
STVREN = ON 0xFF Stack full/underflow will cause Reset.
DEBUG -- Debugger Enable bit (bitmask:0x20)
DEBUG = ON 0xDF Background debugger enabled.
DEBUG = OFF 0xFF Background debugger disabled.
XINST -- Extended Instruction Set Enable bit (bitmask:0x80)
XINST = ON 0x7F Extended Instruction Set and Indexed Addressing Mode enabled.
XINST = OFF 0xFF Extended Instruction Set and Indexed Addressing Mode disabled.
CONFIG3L (address:0x300004, mask:0x7F, default:0x7F)
WDTCPS -- WDT Period Select bits (bitmask:0x1F)
WDTCPS = WDTCPS_0 0xE0 Divider ratio 1:32.
WDTCPS = WDTCPS_1 0xE1 Divider ratio 1:64.
WDTCPS = WDTCPS_2 0xE2 Divider ratio 1:128.
WDTCPS = WDTCPS_3 0xE3 Divider ratio 1:256.
WDTCPS = WDTCPS_4 0xE4 Divider ratio 1:512.
WDTCPS = WDTCPS_5 0xE5 Divider ratio 1:1024.
WDTCPS = WDTCPS_6 0xE6 Divider ratio 1:2048.
WDTCPS = WDTCPS_7 0xE7 Divider ratio 1:4096.
WDTCPS = WDTCPS_8 0xE8 Divider ratio 1:8192.
WDTCPS = WDTCPS_9 0xE9 Divider ratio 1:16384.
WDTCPS = WDTCPS_10 0xEA Divider ratio 1:32768.
WDTCPS = WDTCPS_11 0xEB Divider ratio 1:65536.
WDTCPS = WDTCPS_12 0xEC Divider ratio 1:131072.
WDTCPS = WDTCPS_13 0xED Divider ratio 1:262144.
WDTCPS = WDTCPS_14 0xEE Divider ratio 1:524299.
WDTCPS = WDTCPS_15 0xEF Divider ratio 1:1048576.
WDTCPS = WDTCPS_16 0xF0 Divider ratio 1:2097152.
WDTCPS = WDTCPS_17 0xF1 Divider ratio 1:4194304.
WDTCPS = WDTCPS_18 0xF2 Divider ratio 1:8388608.
WDTCPS = WDTCPS_19 0xF3 Divider ratio 1:32.
WDTCPS = WDTCPS_20 0xF4 Divider ratio 1:32.
WDTCPS = WDTCPS_21 0xF5 Divider ratio 1:32.
WDTCPS = WDTCPS_22 0xF6 Divider ratio 1:32.
WDTCPS = WDTCPS_23 0xF7 Divider ratio 1:32.
WDTCPS = WDTCPS_24 0xF8 Divider ratio 1:32.
WDTCPS = WDTCPS_25 0xF9 Divider ratio 1:32.
WDTCPS = WDTCPS_26 0xFA Divider ratio 1:32.
WDTCPS = WDTCPS_27 0xFB Divider ratio 1:32.
WDTCPS = WDTCPS_28 0xFC Divider ratio 1:32.
WDTCPS = WDTCPS_29 0xFD Divider ratio 1:32.
WDTCPS = WDTCPS_30 0xFE Divider ratio 1:32.
WDTCPS = WDTCPS_31 0xFF Divider ratio 1:65536; software control of WDTPS.
WDTE -- WDT operating mode (bitmask:0x60)
WDTE = OFF 0x9F WDT Disabled.
WDTE = SWDTEN 0xBF WDT enabled/disabled by SWDTEN bit.
WDTE = NSLEEP 0xDF WDT enabled while sleep=0, suspended when sleep=1.
WDTE = ON 0xFF WDT enabled regardless of sleep.
CONFIG3H (address:0x300005, mask:0x3F, default:0x3F)
WDTCWS -- WDT Window Select bits (bitmask:0x07)
WDTCWS = WDTCWS_0 0xF8 window delay = 87.5; no software control; keyed access required.
WDTCWS = WDTCWS_1 0xF9 window delay = 75 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_2 0xFA window delay = 62.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_3 0xFB window delay = 50 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_4 0xFC window delay = 37.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_5 0xFD window delay = 25 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_6 0xFE window always open (100%); no software control; keyed access required.
WDTCWS = WDTCWS_7 0xFF window always open (100%); software control; keyed access not required.
WDTCCS -- WDT input clock selector (bitmask:0x38)
WDTCCS = LFINTOSC 0xC7 WDT reference clock is the 31.0 kHz LFINTOSC.
WDTCCS = HFINTOSC 0xCF WDT reference clock is the 31.2kHz HFINTOSC output.
WDTCCS = SC 0xFF Software Control.
CONFIG4L (address:0x300006, mask:0x0F, default:0x0F)
WRT0 -- Write Protection Block 0 (bitmask:0x01)
WRT0 = ON 0xFE Block 0 (000800-001FFFh) write-protected.
WRT0 = OFF 0xFF Block 0 (000800-001FFFh) not write-protected.
WRT1 -- Write Protection Block 1 (bitmask:0x02)
WRT1 = ON 0xFD Block 1 (002000-003FFFh) write-protected.
WRT1 = OFF 0xFF Block 1 (002000-003FFFh) not write-protected.
WRT2 -- Write Protection Block 2 (bitmask:0x04)
WRT2 = ON 0xFB Block 2 (004000-005FFFh) write-protected.
WRT2 = OFF 0xFF Block 2 (004000-005FFFh) not write-protected.
WRT3 -- Write Protection Block 3 (bitmask:0x08)
WRT3 = ON 0xF7 Block 3 (006000-007FFFh) write-protected.
WRT3 = OFF 0xFF Block 3 (006000-007FFFh) not write-protected.
CONFIG4H (address:0x300007, mask:0x37, default:0x37)
WRTC -- Configuration Register Write Protection bit (bitmask:0x01)
WRTC = ON 0xFE Configuration registers (300000-30000Bh) write-protected.
WRTC = OFF 0xFF Configuration registers (300000-30000Bh) not write-protected.
WRTB -- Boot Block Write Protection bit (bitmask:0x02)
WRTB = ON 0xFD Boot Block (000000-0007FFh) write-protected.
WRTB = OFF 0xFF Boot Block (000000-0007FFh) not write-protected.
WRTD -- Data EEPROM Write Protection bit (bitmask:0x04)
WRTD = ON 0xFB Data EEPROM write-protected.
WRTD = OFF 0xFF Data EEPROM not write-protected.
SCANE -- Scanner Enable bit (bitmask:0x10)
SCANE = OFF 0xEF Scanner module is NOT available for use, SCANMD bit is ignored.
SCANE = ON 0xFF Scanner module is available for use, SCANMD bit can control the module.
LVP -- Low Voltage Programming Enable bit (bitmask:0x20)
LVP = OFF 0xDF HV on MCLR/VPP must be used for programming.
LVP = ON 0xFF Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
CONFIG5L (address:0x300008, mask:0x03, default:0x03)
CP -- UserNVM Program Memory Code Protection bit (bitmask:0x01)
CP = ON 0xFE UserNVM code protection enabled.
CP = OFF 0xFF UserNVM code protection disabled.
CPD -- DataNVM Memory Code Protection bit (bitmask:0x02)
CPD = ON 0xFD DataNVM code protection enabled.
CPD = OFF 0xFF DataNVM code protection disabled.
CONFIG6L (address:0x30000A, mask:0x0F, default:0x0F)
EBTR0 -- Table Read Protection Block 0 (bitmask:0x01)
EBTR0 = ON 0xFE Block 0 (000800-001FFFh) protected from table reads executed in other blocks.
EBTR0 = OFF 0xFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks.
EBTR1 -- Table Read Protection Block 1 (bitmask:0x02)
EBTR1 = ON 0xFD Block 1 (002000-003FFFh) protected from table reads executed in other blocks.
EBTR1 = OFF 0xFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks.
EBTR2 -- Table Read Protection Block 2 (bitmask:0x04)
EBTR2 = ON 0xFB Block 2 (004000-005FFFh) protected from table reads executed in other blocks.
EBTR2 = OFF 0xFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks.
EBTR3 -- Table Read Protection Block 3 (bitmask:0x08)
EBTR3 = ON 0xF7 Block 3 (006000-007FFFh) protected from table reads executed in other blocks.
EBTR3 = OFF 0xFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks.
CONFIG6H (address:0x30000B, mask:0x02, default:0x02)
EBTRB -- Boot Block Table Read Protection bit (bitmask:0x02)
EBTRB = ON 0xFD Boot Block (000000-0007FFh) protected from table reads executed in other blocks.
EBTRB = OFF 0xFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:49 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.