All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18F25K50
CONFIG1L (address:0x300000, mask:0x3B, default:0x00)
PLLSEL -- PLL Selection (bitmask:0x01)
PLLSEL = PLL4X 0xFE 4x clock multiplier.
PLLSEL = PLL3X 0xFF 3x clock multiplier.
CFGPLLEN -- PLL Enable Configuration bit (bitmask:0x02)
CFGPLLEN = OFF 0xFD PLL Disabled (firmware controlled).
CFGPLLEN = ON 0xFF PLL Enabled.
CPUDIV -- CPU System Clock Postscaler (bitmask:0x18)
CPUDIV = NOCLKDIV 0xE7 CPU uses system clock (no divide).
CPUDIV = CLKDIV2 0xEF CPU uses system clock divided by 2.
CPUDIV = CLKDIV3 0xF7 CPU uses system clock divided by 3.
CPUDIV = CLKDIV6 0xFF CPU uses system clock divided by 6.
LS48MHZ -- Low Speed USB mode with 48 MHz system clock (bitmask:0x20)
LS48MHZ = SYS24X4 0xDF System clock at 24 MHz, USB clock divider is set to 4.
LS48MHZ = SYS48X8 0xFF System clock at 48 MHz, USB clock divider is set to 8.
CONFIG1H (address:0x300001, mask:0xEF, default:0x25)
FOSC -- Oscillator Selection (bitmask:0x0F)
FOSC = LP 0xF0 LP oscillator.
FOSC = XT 0xF1 XT oscillator.
FOSC = HSH 0xF2 HS oscillator, high power 16MHz to 25MHz.
FOSC = HSM 0xF3 HS oscillator, medium power 4MHz to 16MHz.
FOSC = ECHCLKO 0xF4 EC oscillator, high power 16MHz to 48MHz, clock output on OSC2.
FOSC = ECHIO 0xF5 EC oscillator, high power 16MHz to 48MHz.
FOSC = RCCLKO 0xF6 External RC oscillator, clock output on OSC2.
FOSC = RCIO 0xF7 External RC oscillator.
FOSC = INTOSCIO 0xF8 Internal oscillator.
FOSC = INTOSCCLKO 0xF9 Internal oscillator, clock output on OSC2.
FOSC = ECMCLKO 0xFA EC oscillator, medium power 4MHz to 16MHz, clock output on OSC2.
FOSC = ECMIO 0xFB EC oscillator, medium power 4MHz to 16MHz.
FOSC = ECLCLKO 0xFC EC oscillator, low power <4MHz, clock output on OSC2.
FOSC = ECLIO 0xFD EC oscillator, low power <4MHz.
PCLKEN -- Primary Oscillator Shutdown (bitmask:0x20)
PCLKEN = OFF 0xDF Primary oscillator shutdown firmware controlled.
PCLKEN = ON 0xFF Primary oscillator enabled.
FCMEN -- Fail-Safe Clock Monitor (bitmask:0x40)
FCMEN = OFF 0xBF Fail-Safe Clock Monitor disabled.
FCMEN = ON 0xFF Fail-Safe Clock Monitor enabled.
IESO -- Internal/External Oscillator Switchover (bitmask:0x80)
IESO = OFF 0x7F Oscillator Switchover mode disabled.
IESO = ON 0xFF Oscillator Switchover mode enabled.
CONFIG2L (address:0x300002, mask:0x5F, default:0x5F)
PWRTEN -- Power-up Timer Enable (bitmask:0x01)
PWRTEN = ON 0xFE Power up timer enabled.
PWRTEN = OFF 0xFF Power up timer disabled.
BOREN -- Brown-out Reset Enable (bitmask:0x06)
BOREN = OFF 0xF9 BOR disabled in hardware (SBOREN is ignored).
BOREN = ON 0xFB BOR controlled by firmware (SBOREN is enabled).
BOREN = NOSLP 0xFD BOR enabled in hardware, disabled in Sleep mode (SBOREN is ignored).
BOREN = SBORDIS 0xFF BOR enabled in hardware (SBOREN is ignored).
BORV -- Brown-out Reset Voltage (bitmask:0x18)
BORV = 285 0xE7 BOR set to 2.85V nominal.
BORV = 250 0xEF BOR set to 2.5V nominal.
BORV = 220 0xF7 BOR set to 2.2V nominal.
BORV = 190 0xFF BOR set to 1.9V nominal.
LPBOR -- Low-Power Brown-out Reset (bitmask:0x40)
LPBOR = ON 0xBF Low-Power Brown-out Reset enabled.
LPBOR = OFF 0xFF Low-Power Brown-out Reset disabled.
CONFIG2H (address:0x300003, mask:0x3F, default:0x3F)
WDTEN -- Watchdog Timer Enable bits (bitmask:0x03)
WDTEN = OFF 0xFC WDT disabled in hardware (SWDTEN ignored).
WDTEN = NOSLP 0xFD WDT enabled in hardware, disabled in Sleep mode (SWDTEN ignored).
WDTEN = SWON 0xFE WDT controlled by firmware (SWDTEN enabled).
WDTEN = ON 0xFF WDT enabled in hardware (SWDTEN ignored).
WDTPS -- Watchdog Timer Postscaler (bitmask:0x3C)
WDTPS = 1 0xC3 1:1.
WDTPS = 2 0xC7 1:2.
WDTPS = 4 0xCB 1:4.
WDTPS = 8 0xCF 1:8.
WDTPS = 16 0xD3 1:16.
WDTPS = 32 0xD7 1:32.
WDTPS = 64 0xDB 1:64.
WDTPS = 128 0xDF 1:128.
WDTPS = 256 0xE3 1:256.
WDTPS = 512 0xE7 1:512.
WDTPS = 1024 0xEB 1:1024.
WDTPS = 2048 0xEF 1:2048.
WDTPS = 4096 0xF3 1:4096.
WDTPS = 8192 0xF7 1:8192.
WDTPS = 16384 0xFB 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3H (address:0x300005, mask:0xD3, default:0xD3)
CCP2MX -- CCP2 MUX bit (bitmask:0x01)
CCP2MX = RB3 0xFE CCP2 input/output is multiplexed with RB3.
CCP2MX = RC1 0xFF CCP2 input/output is multiplexed with RC1.
PBADEN -- PORTB A/D Enable bit (bitmask:0x02)
PBADEN = OFF 0xFD PORTB<5:0> pins are configured as digital I/O on Reset.
PBADEN = ON 0xFF PORTB<5:0> pins are configured as analog input channels on Reset.
T3CMX -- Timer3 Clock Input MUX bit (bitmask:0x10)
T3CMX = RB5 0xEF T3CKI function is on RB5.
T3CMX = RC0 0xFF T3CKI function is on RC0.
SDOMX -- SDO Output MUX bit (bitmask:0x40)
SDOMX = RC7 0xBF SDO function is on RC7.
SDOMX = RB3 0xFF SDO function is on RB3.
MCLRE -- Master Clear Reset Pin Enable (bitmask:0x80)
MCLRE = OFF 0x7F RE3 input pin enabled; external MCLR disabled.
MCLRE = ON 0xFF MCLR pin enabled; RE3 input disabled.
CONFIG4L (address:0x300006, mask:0xE5, default:0x85)
STVREN -- Stack Full/Underflow Reset (bitmask:0x01)
STVREN = OFF 0xFE Stack full/underflow will not cause Reset.
STVREN = ON 0xFF Stack full/underflow will cause Reset.
LVP -- Single-Supply ICSP Enable bit (bitmask:0x04)
LVP = OFF 0xFB Single-Supply ICSP disabled.
LVP = ON 0xFF Single-Supply ICSP enabled if MCLRE is also 1.
ICPRT -- Dedicated In-Circuit Debug/Programming Port Enable (bitmask:0x20)
ICPRT = OFF 0xDF ICPORT disabled.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF 0xBF Instruction set extension and Indexed Addressing mode disabled.
XINST = ON 0xFF Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON 0x7F Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF 0xFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x0F, default:0x0F)
CP0 -- Block 0 Code Protect (bitmask:0x01)
CP0 = ON 0xFE Block 0 is code-protected.
CP0 = OFF 0xFF Block 0 is not code-protected.
CP1 -- Block 1 Code Protect (bitmask:0x02)
CP1 = ON 0xFD Block 1 is code-protected.
CP1 = OFF 0xFF Block 1 is not code-protected.
CP2 -- Block 2 Code Protect (bitmask:0x04)
CP2 = ON 0xFB Block 2 is code-protected.
CP2 = OFF 0xFF Block 2 is not code-protected.
CP3 -- Block 3 Code Protect (bitmask:0x08)
CP3 = ON 0xF7 Block 3 is code-protected.
CP3 = OFF 0xFF Block 3 is not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)
CPB -- Boot Block Code Protect (bitmask:0x40)
CPB = ON 0xBF Boot block is code-protected.
CPB = OFF 0xFF Boot block is not code-protected.
CPD -- Data EEPROM Code Protect (bitmask:0x80)
CPD = ON 0x7F Data EEPROM is code-protected.
CPD = OFF 0xFF Data EEPROM is not code-protected.
CONFIG6L (address:0x30000A, mask:0x0F, default:0x0F)
WRT0 -- Block 0 Write Protect (bitmask:0x01)
WRT0 = ON 0xFE Block 0 (0800-1FFFh) is write-protected.
WRT0 = OFF 0xFF Block 0 (0800-1FFFh) is not write-protected.
WRT1 -- Block 1 Write Protect (bitmask:0x02)
WRT1 = ON 0xFD Block 1 (2000-3FFFh) is write-protected.
WRT1 = OFF 0xFF Block 1 (2000-3FFFh) is not write-protected.
WRT2 -- Block 2 Write Protect (bitmask:0x04)
WRT2 = ON 0xFB Block 2 (04000-5FFFh) is write-protected.
WRT2 = OFF 0xFF Block 2 (04000-5FFFh) is not write-protected.
WRT3 -- Block 3 Write Protect (bitmask:0x08)
WRT3 = ON 0xF7 Block 3 (06000-7FFFh) is write-protected.
WRT3 = OFF 0xFF Block 3 (06000-7FFFh) is not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)
WRTC -- Configuration Registers Write Protect (bitmask:0x20)
WRTC = ON 0xDF Configuration registers (300000-3000FFh) are write-protected.
WRTC = OFF 0xFF Configuration registers (300000-3000FFh) are not write-protected.
WRTB -- Boot Block Write Protect (bitmask:0x40)
WRTB = ON 0xBF Boot block (0000-7FFh) is write-protected.
WRTB = OFF 0xFF Boot block (0000-7FFh) is not write-protected.
WRTD -- Data EEPROM Write Protect (bitmask:0x80)
WRTD = ON 0x7F Data EEPROM is write-protected.
WRTD = OFF 0xFF Data EEPROM is not write-protected.
CONFIG7L (address:0x30000C, mask:0x0F, default:0x0F)
EBTR0 -- Block 0 Table Read Protect (bitmask:0x01)
EBTR0 = ON 0xFE Block 0 is protected from table reads executed in other blocks.
EBTR0 = OFF 0xFF Block 0 is not protected from table reads executed in other blocks.
EBTR1 -- Block 1 Table Read Protect (bitmask:0x02)
EBTR1 = ON 0xFD Block 1 is protected from table reads executed in other blocks.
EBTR1 = OFF 0xFF Block 1 is not protected from table reads executed in other blocks.
EBTR2 -- Block 2 Table Read Protect (bitmask:0x04)
EBTR2 = ON 0xFB Block 2 is protected from table reads executed in other blocks.
EBTR2 = OFF 0xFF Block 2 is not protected from table reads executed in other blocks.
EBTR3 -- Block 3 Table Read Protect (bitmask:0x08)
EBTR3 = ON 0xF7 Block 3 is protected from table reads executed in other blocks.
EBTR3 = OFF 0xFF Block 3 is not protected from table reads executed in other blocks.
CONFIG7H (address:0x30000D, mask:0x40, default:0x40)
EBTRB -- Boot Block Table Read Protect (bitmask:0x40)
EBTRB = ON 0xBF Boot block is protected from table reads executed in other blocks.
EBTRB = OFF 0xFF Boot block is not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:49 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.