PIC18F26K22 | ||||
---|---|---|---|---|
CONFIG1H (address:0x300001, mask:0xFF, default:0x25) | ||||
FOSC -- Oscillator Selection bits (bitmask:0x0F) | ||||
FOSC = LP | 0xF0 | LP oscillator. | ||
FOSC = XT | 0xF1 | XT oscillator. | ||
FOSC = HSHP | 0xF2 | HS oscillator (high power > 16 MHz). | ||
FOSC = HSMP | 0xF3 | HS oscillator (medium power 4-16 MHz). | ||
FOSC = ECHP | 0xF4 | EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz). | ||
FOSC = ECHPIO6 | 0xF5 | EC oscillator (high power, >16 MHz). | ||
FOSC = RC | 0xF6 | External RC oscillator, CLKOUT function on OSC2. | ||
FOSC = RCIO6 | 0xF7 | External RC oscillator. | ||
FOSC = INTIO67 | 0xF8 | Internal oscillator block. | ||
FOSC = INTIO7 | 0xF9 | Internal oscillator block, CLKOUT function on OSC2. | ||
FOSC = ECMP | 0xFA | EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz). | ||
FOSC = ECMPIO6 | 0xFB | EC oscillator (medium power, 500 kHz-16 MHz). | ||
FOSC = ECLP | 0xFC | EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz). | ||
FOSC = ECLPIO6 | 0xFD | EC oscillator (low power, <500 kHz). | ||
PLLCFG -- 4X PLL Enable (bitmask:0x10) | ||||
PLLCFG = OFF | 0xEF | Oscillator used directly. | ||
PLLCFG = ON | 0xFF | Oscillator multiplied by 4. | ||
PRICLKEN -- Primary clock enable bit (bitmask:0x20) | ||||
PRICLKEN = OFF | 0xDF | Primary clock can be disabled by software. | ||
PRICLKEN = ON | 0xFF | Primary clock enabled. | ||
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40) | ||||
FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled. | ||
FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled. | ||
IESO -- Internal/External Oscillator Switchover bit (bitmask:0x80) | ||||
IESO = OFF | 0x7F | Oscillator Switchover mode disabled. | ||
IESO = ON | 0xFF | Oscillator Switchover mode enabled. | ||
CONFIG2L (address:0x300002, mask:0x1F, default:0x1F) | ||||
PWRTEN -- Power-up Timer Enable bit (bitmask:0x01) | ||||
PWRTEN = ON | 0xFE | Power up timer enabled. | ||
PWRTEN = OFF | 0xFF | Power up timer disabled. | ||
BOREN -- Brown-out Reset Enable bits (bitmask:0x06) | ||||
BOREN = OFF | 0xF9 | Brown-out Reset disabled in hardware and software. | ||
BOREN = ON | 0xFB | Brown-out Reset enabled and controlled by software (SBOREN is enabled). | ||
BOREN = NOSLP | 0xFD | Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). | ||
BOREN = SBORDIS | 0xFF | Brown-out Reset enabled in hardware only (SBOREN is disabled). | ||
BORV -- Brown Out Reset Voltage bits (bitmask:0x18) | ||||
BORV = 285 | 0xE7 | VBOR set to 2.85 V nominal. | ||
BORV = 250 | 0xEF | VBOR set to 2.50 V nominal. | ||
BORV = 220 | 0xF7 | VBOR set to 2.20 V nominal. | ||
BORV = 190 | 0xFF | VBOR set to 1.90 V nominal. | ||
CONFIG2H (address:0x300003, mask:0x3F, default:0x3F) | ||||
WDTEN -- Watchdog Timer Enable bits (bitmask:0x03) | ||||
WDTEN = OFF | 0xFC | Watch dog timer is always disabled. SWDTEN has no effect. | ||
WDTEN = NOSLP | 0xFD | WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect. | ||
WDTEN = SWON | 0xFE | WDT is controlled by SWDTEN bit of the WDTCON register. | ||
WDTEN = ON | 0xFF | WDT is always enabled. SWDTEN bit has no effect. | ||
WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x3C) | ||||
WDTPS = 1 | 0xC3 | 1:1. | ||
WDTPS = 2 | 0xC7 | 1:2. | ||
WDTPS = 4 | 0xCB | 1:4. | ||
WDTPS = 8 | 0xCF | 1:8. | ||
WDTPS = 16 | 0xD3 | 1:16. | ||
WDTPS = 32 | 0xD7 | 1:32. | ||
WDTPS = 64 | 0xDB | 1:64. | ||
WDTPS = 128 | 0xDF | 1:128. | ||
WDTPS = 256 | 0xE3 | 1:256. | ||
WDTPS = 512 | 0xE7 | 1:512. | ||
WDTPS = 1024 | 0xEB | 1:1024. | ||
WDTPS = 2048 | 0xEF | 1:2048. | ||
WDTPS = 4096 | 0xF3 | 1:4096. | ||
WDTPS = 8192 | 0xF7 | 1:8192. | ||
WDTPS = 16384 | 0xFB | 1:16384. | ||
WDTPS = 32768 | 0xFF | 1:32768. | ||
CONFIG3H (address:0x300005, mask:0xBF, default:0xBF) | ||||
CCP2MX -- CCP2 MUX bit (bitmask:0x01) | ||||
CCP2MX = PORTB3 | 0xFE | CCP2 input/output is multiplexed with RB3. | ||
CCP2MX = PORTC1 | 0xFF | CCP2 input/output is multiplexed with RC1. | ||
PBADEN -- PORTB A/D Enable bit (bitmask:0x02) | ||||
PBADEN = OFF | 0xFD | PORTB<5:0> pins are configured as digital I/O on Reset. | ||
PBADEN = ON | 0xFF | PORTB<5:0> pins are configured as analog input channels on Reset. | ||
CCP3MX -- P3A/CCP3 Mux bit (bitmask:0x04) | ||||
CCP3MX = PORTC6 | 0xFB | P3A/CCP3 input/output is mulitplexed with RC6. | ||
CCP3MX = PORTB5 | 0xFF | P3A/CCP3 input/output is multiplexed with RB5. | ||
HFOFST -- HFINTOSC Fast Start-up (bitmask:0x08) | ||||
HFOFST = OFF | 0xF7 | HFINTOSC output and ready status are delayed by the oscillator stable status. | ||
HFOFST = ON | 0xFF | HFINTOSC output and ready status are not delayed by the oscillator stable status. | ||
T3CMX -- Timer3 Clock input mux bit (bitmask:0x10) | ||||
T3CMX = PORTB5 | 0xEF | T3CKI is on RB5. | ||
T3CMX = PORTC0 | 0xFF | T3CKI is on RC0. | ||
P2BMX -- ECCP2 B output mux bit (bitmask:0x20) | ||||
P2BMX = PORTC0 | 0xDF | P2B is on RC0. | ||
P2BMX = PORTB5 | 0xFF | P2B is on RB5. | ||
MCLRE -- MCLR Pin Enable bit (bitmask:0x80) | ||||
MCLRE = INTMCLR | 0x7F | RE3 input pin enabled; MCLR disabled. | ||
MCLRE = EXTMCLR | 0xFF | MCLR pin enabled, RE3 input pin disabled. | ||
CONFIG4L (address:0x300006, mask:0xC5, default:0x85) | ||||
STVREN -- Stack Full/Underflow Reset Enable bit (bitmask:0x01) | ||||
STVREN = OFF | 0xFE | Stack full/underflow will not cause Reset. | ||
STVREN = ON | 0xFF | Stack full/underflow will cause Reset. | ||
LVP -- Single-Supply ICSP Enable bit (bitmask:0x04) | ||||
LVP = OFF | 0xFB | Single-Supply ICSP disabled. | ||
LVP = ON | 0xFF | Single-Supply ICSP enabled if MCLRE is also 1. | ||
XINST -- Extended Instruction Set Enable bit (bitmask:0x40) | ||||
XINST = OFF | 0xBF | Instruction set extension and Indexed Addressing mode disabled (Legacy mode). | ||
XINST = ON | 0xFF | Instruction set extension and Indexed Addressing mode enabled. | ||
DEBUG -- Background Debug (bitmask:0x80) | ||||
DEBUG = ON | 0x7F | Enabled. | ||
DEBUG = OFF | 0xFF | Disabled. | ||
CONFIG5L (address:0x300008, mask:0x0F, default:0x0F) | ||||
CP0 -- Code Protection Block 0 (bitmask:0x01) | ||||
CP0 = ON | 0xFE | Block 0 (000800-003FFFh) code-protected. | ||
CP0 = OFF | 0xFF | Block 0 (000800-003FFFh) not code-protected. | ||
CP1 -- Code Protection Block 1 (bitmask:0x02) | ||||
CP1 = ON | 0xFD | Block 1 (004000-007FFFh) code-protected. | ||
CP1 = OFF | 0xFF | Block 1 (004000-007FFFh) not code-protected. | ||
CP2 -- Code Protection Block 2 (bitmask:0x04) | ||||
CP2 = ON | 0xFB | Block 2 (008000-00BFFFh) code-protected. | ||
CP2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not code-protected. | ||
CP3 -- Code Protection Block 3 (bitmask:0x08) | ||||
CP3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) code-protected. | ||
CP3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not code-protected. | ||
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0) | ||||
CPB -- Boot Block Code Protection bit (bitmask:0x40) | ||||
CPB = ON | 0xBF | Boot block (000000-0007FFh) code-protected. | ||
CPB = OFF | 0xFF | Boot block (000000-0007FFh) not code-protected. | ||
CPD -- Data EEPROM Code Protection bit (bitmask:0x80) | ||||
CPD = ON | 0x7F | Data EEPROM code-protected. | ||
CPD = OFF | 0xFF | Data EEPROM not code-protected. | ||
CONFIG6L (address:0x30000A, mask:0x0F, default:0x0F) | ||||
WRT0 -- Write Protection Block 0 (bitmask:0x01) | ||||
WRT0 = ON | 0xFE | Block 0 (000800-003FFFh) write-protected. | ||
WRT0 = OFF | 0xFF | Block 0 (000800-003FFFh) not write-protected. | ||
WRT1 -- Write Protection Block 1 (bitmask:0x02) | ||||
WRT1 = ON | 0xFD | Block 1 (004000-007FFFh) write-protected. | ||
WRT1 = OFF | 0xFF | Block 1 (004000-007FFFh) not write-protected. | ||
WRT2 -- Write Protection Block 2 (bitmask:0x04) | ||||
WRT2 = ON | 0xFB | Block 2 (008000-00BFFFh) write-protected. | ||
WRT2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not write-protected. | ||
WRT3 -- Write Protection Block 3 (bitmask:0x08) | ||||
WRT3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) write-protected. | ||
WRT3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not write-protected. | ||
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0) | ||||
WRTC -- Configuration Register Write Protection bit (bitmask:0x20) | ||||
WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) write-protected. | ||
WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) not write-protected. | ||
WRTB -- Boot Block Write Protection bit (bitmask:0x40) | ||||
WRTB = ON | 0xBF | Boot Block (000000-0007FFh) write-protected. | ||
WRTB = OFF | 0xFF | Boot Block (000000-0007FFh) not write-protected. | ||
WRTD -- Data EEPROM Write Protection bit (bitmask:0x80) | ||||
WRTD = ON | 0x7F | Data EEPROM write-protected. | ||
WRTD = OFF | 0xFF | Data EEPROM not write-protected. | ||
CONFIG7L (address:0x30000C, mask:0x0F, default:0x0F) | ||||
EBTR0 -- Table Read Protection Block 0 (bitmask:0x01) | ||||
EBTR0 = ON | 0xFE | Block 0 (000800-003FFFh) protected from table reads executed in other blocks. | ||
EBTR0 = OFF | 0xFF | Block 0 (000800-003FFFh) not protected from table reads executed in other blocks. | ||
EBTR1 -- Table Read Protection Block 1 (bitmask:0x02) | ||||
EBTR1 = ON | 0xFD | Block 1 (004000-007FFFh) protected from table reads executed in other blocks. | ||
EBTR1 = OFF | 0xFF | Block 1 (004000-007FFFh) not protected from table reads executed in other blocks. | ||
EBTR2 -- Table Read Protection Block 2 (bitmask:0x04) | ||||
EBTR2 = ON | 0xFB | Block 2 (008000-00BFFFh) protected from table reads executed in other blocks. | ||
EBTR2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks. | ||
EBTR3 -- Table Read Protection Block 3 (bitmask:0x08) | ||||
EBTR3 = ON | 0xF7 | Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks. | ||
EBTR3 = OFF | 0xFF | Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks. | ||
CONFIG7H (address:0x30000D, mask:0x40, default:0x40) | ||||
EBTRB -- Boot Block Table Read Protection bit (bitmask:0x40) | ||||
EBTRB = ON | 0xBF | Boot Block (000000-0007FFh) protected from table reads executed in other blocks. | ||
EBTRB = OFF | 0xFF | Boot Block (000000-0007FFh) not protected from table reads executed in other blocks. |
This page generated automatically by the device-help.pl program (2017-05-13 09:29:49 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.