All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18F4320
CONFIG1H (address:0x300001, mask:0xCF, default:0xCF)
OSC -- Oscillator Selection bits (bitmask:0x0F)
OSC = LP 0xF0 LP Oscillator.
OSC = XT 0xF1 XT Oscillator.
OSC = HS 0xF2 HS Oscillator.
OSC = EC 0xF4 EC oscillator, CLKO function on RA6.
OSC = ECIO 0xF5 EC oscillator, port function on RA6.
OSC = HSPLL 0xF6 HS oscillator, PLL enabled (clock frequency = 4 x FOSC1).
OSC = RCIO 0xF7 External RC oscillator, port function on RA6.
OSC = INTIO2 0xF8 Internal RC oscillator, port function on RA6 and port function on RA7.
OSC = INTIO1 0xF9 Internal RC oscillator, CLKO function on RA6 and port function on RA7.
OSC = RC 0xFC External RC oscillator, CLKO function on RA6.
FSCM -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FSCM = OFF 0xBF Fail-Safe Clock Monitor disabled.
FSCM = ON 0xFF Fail-Safe Clock Monitor enabled.
IESO -- Internal/External Switchover bit (bitmask:0x80)
IESO = OFF 0x7F Internal/External Switchover mode disabled.
IESO = ON 0xFF Internal/External Switchover mode enabled.
CONFIG2L (address:0x300002, mask:0x0F, default:0x0F)
PWRT -- Power-up Timer enable bit (bitmask:0x01)
PWRT = ON 0xFE PWRT enabled.
PWRT = OFF 0xFF PWRT disabled.
BOR -- Brown-out Reset enable bit (bitmask:0x02)
BOR = OFF 0xFD Brown-out Reset disabled.
BOR = ON 0xFF Brown-out Reset enabled.
BORV -- Brown-out Reset Voltage bits (bitmask:0x0C)
BORV = 45 0xF3 VBOR set to 4.5V.
BORV = 42 0xF7 VBOR set to 4.2V.
BORV = 27 0xFB VBOR set to 2.7V.
BORV = 20 0xFF VBOR set to 2.0V.
CONFIG2H (address:0x300003, mask:0x1F, default:0x1F)
WDT -- Watchdog Timer Enable bit (bitmask:0x01)
WDT = OFF 0xFE WDT disabled (control is placed on the SWDTEN bit).
WDT = ON 0xFF WDT enabled.
WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x1E)
WDTPS = 1 0xE1 1:1.
WDTPS = 2 0xE3 1:2.
WDTPS = 4 0xE5 1:4.
WDTPS = 8 0xE7 1:8.
WDTPS = 16 0xE9 1:16.
WDTPS = 32 0xEB 1:32.
WDTPS = 64 0xED 1:64.
WDTPS = 128 0xEF 1:128.
WDTPS = 256 0xF1 1:256.
WDTPS = 512 0xF3 1:512.
WDTPS = 1024 0xF5 1:1024.
WDTPS = 2048 0xF7 1:2048.
WDTPS = 4096 0xF9 1:4096.
WDTPS = 8192 0xFB 1:8192.
WDTPS = 16384 0xFD 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3H (address:0x300005, mask:0x83, default:0x83)
CCP2MX -- CCP2 MUX bit (bitmask:0x01)
CCP2MX = OFF 0xFE CCP2 input/output is multiplexed with RB3.
CCP2MX = ON 0xFF CCP2 input/output is multiplexed with RC1.
PBAD -- PORTB A/D Enable bit (bitmask:0x02)
PBAD = DIG 0xFD PORTB<4:0> pins are configured as digital I/O on Reset.
PBAD = ANA 0xFF PORTB<4:0> pins are configured as analog input channels on Reset.
MCLRE -- MCLR Pin Enable bit (bitmask:0x80)
MCLRE = OFF 0x7F MCLR disabled; RE3 input is enabled in 40-pin devices only (PIC18F4X20).
MCLRE = ON 0xFF MCLR pin enabled; RE3 input pin disabled.
CONFIG4L (address:0x300006, mask:0x85, default:0x85)
STVR -- Stack Full/Underflow Reset Enable bit (bitmask:0x01)
STVR = OFF 0xFE Stack full/underflow will not cause Reset.
STVR = ON 0xFF Stack full/underflow will cause Reset.
LVP -- Single-Supply ICSP Enable bit (bitmask:0x04)
LVP = OFF 0xFB Single-Supply ICSP disabled.
LVP = ON 0xFF Single-Supply ICSP enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON 0x7F Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF 0xFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x0F, default:0x0F)
CP0 -- Code Protection bit (bitmask:0x01)
CP0 = ON 0xFE Block 0 (000200-0007FFh) code-protected.
CP0 = OFF 0xFF Block 0 (000200-0007FFh) not code-protected.
CP1 -- Code Protection bit (bitmask:0x02)
CP1 = ON 0xFD Block 1 (000800-000FFFh) code-protected.
CP1 = OFF 0xFF Block 1 (000800-000FFFh) not code-protected.
CP2 -- Code Protection bit (bitmask:0x04)
CP2 = ON 0xFB Block 2 (001000-0017FFh) code-protected.
CP2 = OFF 0xFF Block 2 (001000-0017FFh) not code-protected.
CP3 -- Code Protection bit (bitmask:0x08)
CP3 = ON 0xF7 Block 3 (001800-001FFFh) code-protected.
CP3 = OFF 0xFF Block 3 (001800-001FFFh) not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)
CPB -- Boot Block Code Protection bit (bitmask:0x40)
CPB = ON 0xBF Boot block (000000-0001FFh) is code-protected.
CPB = OFF 0xFF Boot block (000000-0001FFh) is not code-protected.
CPD -- Data EEPROM Code Protection bit (bitmask:0x80)
CPD = ON 0x7F Data EEPROM is code-protected.
CPD = OFF 0xFF Data EEPROM is not code-protected.
CONFIG6L (address:0x30000A, mask:0x0F, default:0x0F)
WRT0 -- Write Protection bit (bitmask:0x01)
WRT0 = ON 0xFE Block 0 (000200-0007FFh) write-protected.
WRT0 = OFF 0xFF Block 0 (000200-0007FFh) not write-protected.
WRT1 -- Write Protection bit (bitmask:0x02)
WRT1 = ON 0xFD Block 1 (000800-000FFFh) write-protected.
WRT1 = OFF 0xFF Block 1 (000800-000FFFh) not write-protected.
WRT2 -- Write Protection bit (bitmask:0x04)
WRT2 = ON 0xFB Block 2 (001000-0017FFh) write-protected.
WRT2 = OFF 0xFF Block 2 (001000-0017FFh) not write-protected.
WRT3 -- Write Protection bit (bitmask:0x08)
WRT3 = ON 0xF7 Block 3 (001800-001FFFh) write-protected.
WRT3 = OFF 0xFF Block 3 (001800-001FFFh) not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)
WRTC -- Configuration Register Write Protection bit (bitmask:0x20)
WRTC = ON 0xDF Configuration registers (300000-3000FFh) are write-protected.
WRTC = OFF 0xFF Configuration registers (300000-3000FFh) are not write-protected.
WRTB -- Boot Block Write Protection bit (bitmask:0x40)
WRTB = ON 0xBF Boot block (000000-0001FFh) is write-protected.
WRTB = OFF 0xFF Boot block (000000-0001FFh) is not write-protected.
WRTD -- Data EEPROM Write Protection bit (bitmask:0x80)
WRTD = ON 0x7F Data EEPROM is write-protected.
WRTD = OFF 0xFF Data EEPROM is not write-protected.
CONFIG7L (address:0x30000C, mask:0x0F, default:0x0F)
EBTR0 -- Table Read Protection bit (bitmask:0x01)
EBTR0 = ON 0xFE Block 0 (000200-0007FFh) protected from table reads executed in other blocks.
EBTR0 = OFF 0xFF Block 0 (000200-0007FFh) not protected from table reads executed in other blocks.
EBTR1 -- Table Read Protection bit (bitmask:0x02)
EBTR1 = ON 0xFD Block 1 (000800-000FFFh) protected from table reads executed in other blocks.
EBTR1 = OFF 0xFF Block 1 (000800-000FFFh) not protected from table reads executed in other blocks.
EBTR2 -- Table Read Protection bit (bitmask:0x04)
EBTR2 = ON 0xFB Block 2 (001000-0017FFh) protected from table reads executed in other blocks.
EBTR2 = OFF 0xFF Block 2 (001000-0017FFh) not protected from table reads executed in other blocks.
EBTR3 -- Table Read Protection bit (bitmask:0x08)
EBTR3 = ON 0xF7 Block 3 (001800-001FFFh) protected from table reads executed in other blocks.
EBTR3 = OFF 0xFF Block 3 (001800-001FFFh) not protected from table reads executed in other blocks.
CONFIG7H (address:0x30000D, mask:0x40, default:0x40)
EBTRB -- Boot Block Table Read Protection bit (bitmask:0x40)
EBTRB = ON 0xBF Boot block (000000-0001FFh) is protected from table reads executed in other blocks.
EBTRB = OFF 0xFF Boot block (000000-0001FFh) is not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:50 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.