| PIC18F44J11 | ||||
|---|---|---|---|---|
| CONFIG1L (address:0x003FF8, mask:0xE1, default:0xE1) | ||||
| WDTEN -- Watchdog Timer (bitmask:0x01) | ||||
| WDTEN = OFF | 0x00 | Disabled - Controlled by SWDTEN bit. | ||
| WDTEN = ON | 0x01 | Enabled. | ||
| STVREN -- Stack Overflow/Underflow Reset (bitmask:0x20) | ||||
| STVREN = OFF | 0x00 | Disabled. | ||
| STVREN = ON | 0x20 | Enabled. | ||
| XINST -- Extended Instruction Set (bitmask:0x40) | ||||
| XINST = OFF | 0x00 | Disabled. | ||
| XINST = ON | 0x40 | Enabled. | ||
| DEBUG -- Background Debug (bitmask:0x80) | ||||
| DEBUG = ON | 0x00 | Enabled. | ||
| DEBUG = OFF | 0x80 | Disabled. | ||
| CONFIG1H (address:0x003FF9, mask:0x04, default:0x04) | ||||
| CP0 -- Code Protect (bitmask:0x04) | ||||
| CP0 = ON | 0x00 | Program memory is code-protected. | ||
| CP0 = OFF | 0x04 | Program memory is not code-protected. | ||
| CONFIG2L (address:0x003FFA, mask:0xDF, default:0xDF) | ||||
| OSC -- Oscillator (bitmask:0x07) | ||||
| OSC = INTOSC | 0x00 | INTOSC. | ||
| OSC = INTOSCO | 0x01 | INTOSCO (CLKO-RA6). | ||
| OSC = INTOSCPLL | 0x02 | INTOSCPLL. | ||
| OSC = INTOSCPLLO | 0x03 | INTOSCPLLO (CLKO-RA6). | ||
| OSC = HS | 0x04 | HS. | ||
| OSC = HSPLL | 0x05 | HS+PLL. | ||
| OSC = EC | 0x06 | EC (CLKO-RA6). | ||
| OSC = ECPLL | 0x07 | EC+PLL (CLKO-RA6). | ||
| T1DIG -- T1OSCEN Enforcement (bitmask:0x08) | ||||
| T1DIG = OFF | 0x00 | Secondary Oscillator clock source may not be selected. | ||
| T1DIG = ON | 0x08 | Secondary Oscillator clock source may be selected. | ||
| LPT1OSC -- Low-Power Timer1 Oscillator (bitmask:0x10) | ||||
| LPT1OSC = ON | 0x00 | Low-power operation. | ||
| LPT1OSC = OFF | 0x10 | High-power operation. | ||
| FCMEN -- Fail-Safe Clock Monitor (bitmask:0x40) | ||||
| FCMEN = OFF | 0x00 | Disabled. | ||
| FCMEN = ON | 0x40 | Enabled. | ||
| IESO -- Internal External Oscillator Switch Over Mode (bitmask:0x80) | ||||
| IESO = OFF | 0x00 | Disabled. | ||
| IESO = ON | 0x80 | Enabled. | ||
| CONFIG2H (address:0x003FFB, mask:0x0F, default:0x0F) | ||||
| WDTPS -- Watchdog Postscaler (bitmask:0x0F) | ||||
| WDTPS = 1 | 0x00 | 1:1. | ||
| WDTPS = 2 | 0x01 | 1:2. | ||
| WDTPS = 4 | 0x02 | 1:4. | ||
| WDTPS = 8 | 0x03 | 1:8. | ||
| WDTPS = 16 | 0x04 | 1:16. | ||
| WDTPS = 32 | 0x05 | 1:32. | ||
| WDTPS = 64 | 0x06 | 1:64. | ||
| WDTPS = 128 | 0x07 | 1:128. | ||
| WDTPS = 256 | 0x08 | 1:256. | ||
| WDTPS = 512 | 0x09 | 1:512. | ||
| WDTPS = 1024 | 0x0A | 1:1024. | ||
| WDTPS = 2048 | 0x0B | 1:2048. | ||
| WDTPS = 4096 | 0x0C | 1:4096. | ||
| WDTPS = 8192 | 0x0D | 1:8192. | ||
| WDTPS = 16384 | 0x0E | 1:16384. | ||
| WDTPS = 32768 | 0x0F | 1:32768. | ||
| CONFIG3L (address:0x003FFC, mask:0xFF, default:0xFF) | ||||
| DSWDTOSC -- DSWDT Clock Select (bitmask:0x01) | ||||
| DSWDTOSC = T1OSCREF | 0x00 | DSWDT uses T1OSC/T1CKI. | ||
| DSWDTOSC = INTOSCREF | 0x01 | DSWDT uses INTRC. | ||
| RTCOSC -- RTCC Clock Select (bitmask:0x02) | ||||
| RTCOSC = INTOSCREF | 0x00 | RTCC uses INTRC. | ||
| RTCOSC = T1OSCREF | 0x02 | RTCC uses T1OSC/T1CKI. | ||
| DSBOREN -- Deep Sleep BOR (bitmask:0x04) | ||||
| DSBOREN = OFF | 0x00 | Disabled. | ||
| DSBOREN = ON | 0x04 | Enabled. | ||
| DSWDTEN -- Deep Sleep Watchdog Timer (bitmask:0x08) | ||||
| DSWDTEN = OFF | 0x00 | Disabled. | ||
| DSWDTEN = ON | 0x08 | Enabled. | ||
| DSWDTPS -- Deep Sleep Watchdog Postscaler (bitmask:0xF0) | ||||
| DSWDTPS = 2 | 0x00 | 1:2 (2.1 ms). | ||
| DSWDTPS = 8 | 0x10 | 1:8 (8.3 ms). | ||
| DSWDTPS = 32 | 0x20 | 1:32 (33 ms). | ||
| DSWDTPS = 128 | 0x30 | 1:128 (132 ms). | ||
| DSWDTPS = 512 | 0x40 | 1:512 (528 ms). | ||
| DSWDTPS = 2048 | 0x50 | 1:2,048 (2.1 seconds). | ||
| DSWDTPS = 8192 | 0x60 | 1:8,192 (8.5 seconds). | ||
| DSWDTPS = K32 | 0x70 | 1:32,768 (34 seconds). | ||
| DSWDTPS = K131 | 0x80 | 1:131,072 (135 seconds). | ||
| DSWDTPS = K524 | 0x90 | 1:524,288 (9 minutes). | ||
| DSWDTPS = M2 | 0xA0 | 1:2,097,152 (36 minutes). | ||
| DSWDTPS = M8 | 0xB0 | 1:8,388,608 (2.4 hours). | ||
| DSWDTPS = M33 | 0xC0 | 1:33,554,432 (9.6 hours). | ||
| DSWDTPS = M134 | 0xD0 | 1:134,217,728 (38.5 hours). | ||
| DSWDTPS = M536 | 0xE0 | 1:536,870,912 (6.4 days). | ||
| DSWDTPS = G2 | 0xF0 | 1:2,147,483,648 (25.7 days). | ||
| CONFIG3H (address:0x003FFD, mask:0x09, default:0x09) | ||||
| IOL1WAY -- IOLOCK One-Way Set Enable bit (bitmask:0x01) | ||||
| IOL1WAY = OFF | 0x00 | The IOLOCK bit (PPSCON<0>) can be set and cleared as needed. | ||
| IOL1WAY = ON | 0x01 | The IOLOCK bit (PPSCON<0>) can be set once. | ||
| MSSP7B_EN -- MSSP address masking (bitmask:0x08) | ||||
| MSSP7B_EN = MSK5 | 0x00 | 5 Bit address masking mode. | ||
| MSSP7B_EN = MSK7 | 0x08 | 7 Bit address masking mode. | ||
| CONFIG4L (address:0x003FFE, mask:0xCF, default:0xCF) | ||||
| WPFP -- Write/Erase Protect Page Start/End Location (bitmask:0x0F) | ||||
| WPFP = PAGE_0 | 0x00 | Write Protect Program Flash Page 0. | ||
| WPFP = PAGE_1 | 0x01 | Write Protect Program Flash Page 1. | ||
| WPFP = PAGE_2 | 0x02 | Write Protect Program Flash Page 2. | ||
| WPFP = PAGE_3 | 0x03 | Write Protect Program Flash Page 3. | ||
| WPFP = PAGE_4 | 0x04 | Write Protect Program Flash Page 4. | ||
| WPFP = PAGE_5 | 0x05 | Write Protect Program Flash Page 5. | ||
| WPFP = PAGE_6 | 0x06 | Write Protect Program Flash Page 6. | ||
| WPFP = PAGE_7 | 0x07 | Write Protect Program Flash Page 7. | ||
| WPFP = PAGE_8 | 0x08 | Write Protect Program Flash Page 8. | ||
| WPFP = PAGE_9 | 0x09 | Write Protect Program Flash Page 9. | ||
| WPFP = PAGE_10 | 0x0A | Write Protect Program Flash Page 10. | ||
| WPFP = PAGE_11 | 0x0B | Write Protect Program Flash Page 11. | ||
| WPFP = PAGE_12 | 0x0C | Write Protect Program Flash Page 12. | ||
| WPFP = PAGE_13 | 0x0D | Write Protect Program Flash Page 13. | ||
| WPFP = PAGE_14 | 0x0E | Write Protect Program Flash Page 14. | ||
| WPFP = PAGE_15 | 0x0F | Write Protect Program Flash Page 15. | ||
| WPEND -- Write/Erase Protect Region Select (valid when WPDIS = 0) (bitmask:0x40) | ||||
| WPEND = PAGE_0 | 0x00 | Page 0 through WPFP<5:0> erase/write protected. | ||
| WPEND = PAGE_WPFP | 0x40 | Page WPFP<5:0> through Configuration Words erase/write protected. | ||
| WPCFG -- Write/Erase Protect Configuration Region (bitmask:0x80) | ||||
| WPCFG = ON | 0x00 | Configuration Words page erase/write-protected. | ||
| WPCFG = OFF | 0x80 | Configuration Words page not erase/write-protected. | ||
| CONFIG4H (address:0x003FFF, mask:0x01, default:0x01) | ||||
| WPDIS -- Write Protect Disable bit (bitmask:0x01) | ||||
| WPDIS = ON | 0x00 | WPFP<5:0>/WPEND region erase/write protected. | ||
| WPDIS = OFF | 0x01 | WPFP<5:0>/WPEND region ignored. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:49 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.