PIC18F67J50

PIC18F67J50

CONFIG1L (address:0x01FFF8, mask:0xEF, default:0xEF)

WDTEN -- Watchdog Timer Enable bit (bitmask:0x01)
WDTEN = OFF	0x00	WDT disabled (control is placed on SWDTEN bit).
WDTEN = ON	0x01	WDT enabled.

PLLDIV -- PLL Prescaler Selection bits (bitmask:0x0E)
PLLDIV = 12	0x00	Divide by 12 (48 MHz oscillator input).
PLLDIV = 10	0x02	Divide by 10 (40 MHz oscillator input).
PLLDIV = 6	0x04	Divide by 6 (24 MHz oscillator input).
PLLDIV = 5	0x06	Divide by 5 (20 MHz oscillator input).
PLLDIV = 4	0x08	Divide by 4 (16 MHz oscillator input).
PLLDIV = 3	0x0A	Divide by 3 (12 MHz oscillator input).
PLLDIV = 2	0x0C	Divide by 2 (8 MHz oscillator input).
PLLDIV = 1	0x0E	No prescale (4 MHz oscillator input drives PLL directly).

STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x20)
STVREN = OFF	0x00	Reset on stack overflow/underflow disabled.
STVREN = ON	0x20	Reset on stack overflow/underflow enabled.

XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF	0x00	Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON	0x40	Instruction set extension and Indexed Addressing mode enabled.

DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON	0x00	Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF	0x80	Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.

CONFIG1H (address:0x01FFF9, mask:0x07, default:0x07)

CPUDIV -- CPU System Clock Postscaler (bitmask:0x03)
CPUDIV = OSC4_PLL6	0x00	CPU system clock divide by 6.
CPUDIV = OSC3_PLL3	0x01	CPU system clock divide by 3.
CPUDIV = OSC2_PLL2	0x02	CPU system clock divide by 2.
CPUDIV = OSC1	0x03	No CPU system clock divide.

CP0 -- Code Protection bit (bitmask:0x04)
CP0 = ON	0x00	Program memory is code-protected.
CP0 = OFF	0x04	Program memory is not code-protected.

CONFIG2L (address:0x01FFFA, mask:0xC7, default:0xC7)

FOSC -- Oscillator Selection bits (bitmask:0x07)
FOSC = INTOSC	0x00	INTOSC, Port function on RA6 and RA7.
FOSC = INTOSCO	0x01	INTOSC, CLKO on RA6 and Port function on RA7.
FOSC = INTOSCPLL	0x02	INTOSC with PLL enabled, Port function on RA6 and RA7.
FOSC = INTOSCPLLO	0x03	INTOSC with PLL enabled, CLKO on RA6 and Port function on RA7.
FOSC = HS	0x04	HS oscillator, HS used by USB.
FOSC = HSPLL	0x05	HS oscillator, PLL enabled, HSPLL used by USB.
FOSC = EC	0x06	EC Oscillator with CLKO on RA6, EC used by USB.
FOSC = ECPLL	0x07	EC Oscillator with PLL, CLKO on RA6, ECPLL used by USB.

FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FCMEN = OFF	0x00	Fail-Safe Clock Monitor disabled.
FCMEN = ON	0x40	Fail-Safe Clock Monitor enabled.

IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (bitmask:0x80)
IESO = OFF	0x00	Two-Speed Start-up disabled.
IESO = ON	0x80	Two-Speed Start-up enabled.

CONFIG2H (address:0x01FFFB, mask:0x0F, default:0x0F)

WDTPS -- Watchdog Timer Postscaler Select bits (bitmask:0x0F)
WDTPS = 1	0x00	1:1.
WDTPS = 2	0x01	1:2.
WDTPS = 4	0x02	1:4.
WDTPS = 8	0x03	1:8.
WDTPS = 16	0x04	1:16.
WDTPS = 32	0x05	1:32.
WDTPS = 64	0x06	1:64.
WDTPS = 128	0x07	1:128.
WDTPS = 256	0x08	1:256.
WDTPS = 512	0x09	1:512.
WDTPS = 1024	0x0A	1:1024.
WDTPS = 2048	0x0B	1:2048.
WDTPS = 4096	0x0C	1:4096.
WDTPS = 8192	0x0D	1:8192.
WDTPS = 16384	0x0E	1:16384.
WDTPS = 32768	0x0F	1:32768.

CONFIG3L (address:0x01FFFD, mask:0x09, default:0x09)

CCP2MX -- ECCP2 MUX bit (bitmask:0x01)
CCP2MX = ALTERNATE	0x00	ECCP2/P2A is multiplexed with RE7.
CCP2MX = DEFAULT	0x01	ECCP2/P2A is multiplexed with RC1.

MSSPMSK -- MSSP Address Masking Mode Select bit (bitmask:0x08)
MSSPMSK = MSK5	0x00	5-Bit Address Masking mode enable.
MSSPMSK = MSK7	0x08	7-Bit Address Masking mode enable.

CONFIG1L (address:0x01FFF8, mask:0xEF, default:0xEF)

WDTEN -- Watchdog Timer Enable bit (bitmask:0x01)

WDTEN = OFF

0x00

WDT disabled (control is placed on SWDTEN bit).

WDTEN = ON

0x01

WDT enabled.

PLLDIV -- PLL Prescaler Selection bits (bitmask:0x0E)

PLLDIV = 12

0x00

Divide by 12 (48 MHz oscillator input).

PLLDIV = 10

0x02

Divide by 10 (40 MHz oscillator input).

PLLDIV = 6

0x04

Divide by 6 (24 MHz oscillator input).

PLLDIV = 5

0x06

Divide by 5 (20 MHz oscillator input).

PLLDIV = 4

0x08

Divide by 4 (16 MHz oscillator input).

PLLDIV = 3

0x0A

Divide by 3 (12 MHz oscillator input).

PLLDIV = 2

0x0C

Divide by 2 (8 MHz oscillator input).

PLLDIV = 1

0x0E

No prescale (4 MHz oscillator input drives PLL directly).

STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x20)

STVREN = OFF

0x00

Reset on stack overflow/underflow disabled.

STVREN = ON

0x20

Reset on stack overflow/underflow enabled.

XINST -- Extended Instruction Set Enable bit (bitmask:0x40)

XINST = OFF

0x00

Instruction set extension and Indexed Addressing mode disabled (Legacy mode).

XINST = ON

0x40

Instruction set extension and Indexed Addressing mode enabled.

DEBUG -- Background Debugger Enable bit (bitmask:0x80)

DEBUG = ON

0x00

Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.

DEBUG = OFF

0x80

Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.

CONFIG1H (address:0x01FFF9, mask:0x07, default:0x07)

CPUDIV -- CPU System Clock Postscaler (bitmask:0x03)

CPUDIV = OSC4_PLL6

0x00

CPU system clock divide by 6.

CPUDIV = OSC3_PLL3

0x01

CPU system clock divide by 3.

CPUDIV = OSC2_PLL2

0x02

CPU system clock divide by 2.

CPUDIV = OSC1

0x03

No CPU system clock divide.

CP0 -- Code Protection bit (bitmask:0x04)

CP0 = ON

0x00

Program memory is code-protected.

CP0 = OFF

0x04

Program memory is not code-protected.

CONFIG2L (address:0x01FFFA, mask:0xC7, default:0xC7)

FOSC -- Oscillator Selection bits (bitmask:0x07)

FOSC = INTOSC

0x00

INTOSC, Port function on RA6 and RA7.

FOSC = INTOSCO

0x01

INTOSC, CLKO on RA6 and Port function on RA7.

FOSC = INTOSCPLL

0x02

INTOSC with PLL enabled, Port function on RA6 and RA7.

FOSC = INTOSCPLLO

0x03

INTOSC with PLL enabled, CLKO on RA6 and Port function on RA7.

FOSC = HS

0x04

HS oscillator, HS used by USB.

FOSC = HSPLL

0x05

HS oscillator, PLL enabled, HSPLL used by USB.

FOSC = EC

0x06

EC Oscillator with CLKO on RA6, EC used by USB.

FOSC = ECPLL

0x07

EC Oscillator with PLL, CLKO on RA6, ECPLL used by USB.

FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)

FCMEN = OFF

0x00

Fail-Safe Clock Monitor disabled.

FCMEN = ON

0x40

Fail-Safe Clock Monitor enabled.

IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (bitmask:0x80)

IESO = OFF

0x00

Two-Speed Start-up disabled.

IESO = ON

0x80

Two-Speed Start-up enabled.

CONFIG2H (address:0x01FFFB, mask:0x0F, default:0x0F)

WDTPS -- Watchdog Timer Postscaler Select bits (bitmask:0x0F)

WDTPS = 1

0x00

1:1.

WDTPS = 2

0x01

1:2.

WDTPS = 4

0x02

1:4.

WDTPS = 8

0x03

1:8.

WDTPS = 16

0x04

1:16.

WDTPS = 32

0x05

1:32.

WDTPS = 64

0x06

1:64.

WDTPS = 128

0x07

1:128.

WDTPS = 256

0x08

1:256.

WDTPS = 512

0x09

1:512.

WDTPS = 1024

0x0A

1:1024.

WDTPS = 2048

0x0B

1:2048.

WDTPS = 4096

0x0C

1:4096.

WDTPS = 8192

0x0D

1:8192.

WDTPS = 16384

0x0E

1:16384.

WDTPS = 32768

0x0F

1:32768.

CONFIG3L (address:0x01FFFD, mask:0x09, default:0x09)

CCP2MX -- ECCP2 MUX bit (bitmask:0x01)

CCP2MX = ALTERNATE

0x00

ECCP2/P2A is multiplexed with RE7.

CCP2MX = DEFAULT

0x01

ECCP2/P2A is multiplexed with RC1.

MSSPMSK -- MSSP Address Masking Mode Select bit (bitmask:0x08)

MSSPMSK = MSK5

0x00

5-Bit Address Masking mode enable.

MSSPMSK = MSK7

0x08

7-Bit Address Masking mode enable.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:50 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.