All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
Features Configuration Bits RAM map SFR map
CONFIG1L (address:0x003FF8, mask:0xE1, default:0xE1)
WDTEN -- Watchdog Timer Enable bit (bitmask:0x01)
WDTEN = OFF 0x00 WDT disabled (control is placed on SWDTEN bit).
WDTEN = ON 0x01 WDT enabled.
STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x20)
STVREN = OFF 0x00 Reset on stack overflow/underflow disabled.
STVREN = ON 0x20 Reset on stack overflow/underflow enabled.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF 0x00 Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON 0x40 Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON 0x00 Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF 0x80 Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.
CONFIG1H (address:0x003FF9, mask:0x04, default:0x04)
CP0 -- Code Protection bit (bitmask:0x04)
CP0 = ON 0x00 Program memory is code-protected.
CP0 = OFF 0x04 Program memory is not code-protected.
CONFIG2L (address:0x003FFA, mask:0xC7, default:0xC7)
FOSC -- Oscillator Selection bits (bitmask:0x03)
FOSC = HS 0x00 HS oscillator.
FOSC = HSPLL 0x01 HS oscillator, PLL enabled and under software control.
FOSC = EC 0x02 EC oscillator, CLKO function on OSC2.
FOSC = ECPLL 0x03 EC oscillator, PLL enabled and under software control, CLK function on OSC2.
FOSC2 -- Default/Reset System Clock Select bit (bitmask:0x04)
FOSC2 = OFF 0x00 INTRC enabled as system clock when OSCCON<1:0> = 00.
FOSC2 = ON 0x04 Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FCMEN = OFF 0x00 Fail-Safe Clock Monitor disabled.
FCMEN = ON 0x40 Fail-Safe Clock Monitor enabled.
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (bitmask:0x80)
IESO = OFF 0x00 Two-Speed Start-up disabled.
IESO = ON 0x80 Two-Speed Start-up enabled.
CONFIG2H (address:0x003FFB, mask:0x0F, default:0x0F)
WDTPS -- Watchdog Timer Postscaler Select bits (bitmask:0x0F)
WDTPS = 1 0x00 1:1.
WDTPS = 2 0x01 1:2.
WDTPS = 4 0x02 1:4.
WDTPS = 8 0x03 1:8.
WDTPS = 16 0x04 1:16.
WDTPS = 32 0x05 1:32.
WDTPS = 64 0x06 1:64.
WDTPS = 128 0x07 1:128.
WDTPS = 256 0x08 1:256.
WDTPS = 512 0x09 1:512.
WDTPS = 1024 0x0A 1:1024.
WDTPS = 2048 0x0B 1:2048.
WDTPS = 4096 0x0C 1:4096.
WDTPS = 8192 0x0D 1:8192.
WDTPS = 16384 0x0E 1:16384.
WDTPS = 32768 0x0F 1:32768.
CONFIG3L (address:0x003FFC, mask:0xF8, default:0xF8)
EASHFT -- External Address Bus Shift Enable bit (bitmask:0x08)
EASHFT = OFF 0x00 Address shifting disabled, address on external bus reflects the PC value.
EASHFT = ON 0x08 Address shifting enabled, address on external bus is offset to start at 000000h.
MODE -- External Memory Bus (bitmask:0x30)
MODE = XM20 0x00 Extended Microcontroller mode, 20-bit Address mode.
MODE = XM16 0x10 Extended Microcontroller mode, 16-bit Address mode.
MODE = XM12 0x20 Extended Microcontroller mode, 12-bit Address mode.
MODE = MM 0x30 Microcontroller mode - External bus disabled.
BW -- Data Bus Width Select bit (bitmask:0x40)
BW = 8 0x00 8-bit external bus mode.
BW = 16 0x40 16-bit external bus mode.
WAIT -- External Bus Wait Enable bit (bitmask:0x80)
WAIT = ON 0x00 Wait states for operations on external memory bus enabled.
WAIT = OFF 0x80 Wait states for operations on external memory bus disabled.
CONFIG3H (address:0x003FFD, mask:0x01, default:0x01)
CCP2MX -- CCP2 MUX bit (bitmask:0x01)
CCP2MX = ALTERNATE 0x00 CCP2 is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode.
CCP2MX = DEFAULT 0x01 CCP2 is multiplexed with RC1.

This page generated automatically by the program (2017-05-13 09:29:50 UTC) from the file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.