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Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18F86J72
CONFIG1L (address:0x00FFF8, mask:0x61, default:0x61)
WDTEN -- Watchdog Timer (bitmask:0x01)
WDTEN = OFF 0x00 Disabled-Controlled by SWDTEN bit.
WDTEN = ON 0x01 Enabled.
STVREN -- Stack Overflow Reset (bitmask:0x20)
STVREN = OFF 0x00 Disabled.
STVREN = ON 0x20 Enabled.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF 0x00 Disabled.
XINST = ON 0x40 Enabled.
CONFIG1H (address:0x00FFF9, mask:0x04, default:0x04)
CP0 -- Code Protect (bitmask:0x04)
CP0 = ON 0x00 Enabled.
CP0 = OFF 0x04 Disabled.
CONFIG2L (address:0x00FFFA, mask:0xDF, default:0xDF)
OSC -- Oscillator Selection bits (bitmask:0x07)
OSC = INTOSC 0x00 Internal oscillator, port function on RA6 and RA7 .
OSC = INTOSCPLL 0x01 INTOSC with PLL enabled, port function on RA6 and RA7.
OSC = INTOSCO 0x02 Internal oscillator, CLKOUT on RA6 and port function on RA7.
OSC = INTOSCPLLO 0x03 INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7.
OSC = HS 0x04 HS oscillator.
OSC = HSPLL 0x05 HS oscillator, PLL enabled.
OSC = EC 0x06 EC Oscillator with clock out on RA6.
OSC = ECPLL 0x07 EC Oscillator with PLL.
T1DIG -- Secondary Clock Source T1OSCEN Enforcement (bitmask:0x08)
T1DIG = OFF 0x00 Secondary Oscillator clock source may not be selected.
T1DIG = ON 0x08 Secondary Oscillator clock source may be selected.
LPT1OSC -- Low-Power Timer1 Oscillator Enable bit (bitmask:0x10)
LPT1OSC = ON 0x00 Timer1 oscillator configured for low-power operation.
LPT1OSC = OFF 0x10 Timer1 oscillator configured for higher power operation.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FCMEN = OFF 0x00 Fail-Safe Clock Monitor disabled.
FCMEN = ON 0x40 Fail-Safe Clock Monitor enabled.
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (bitmask:0x80)
IESO = OFF 0x00 Two-Speed Start-up disabled.
IESO = ON 0x80 Two-Speed Start-up enabled.
CONFIG2H (address:0x00FFFB, mask:0x0F, default:0x0F)
WDTPS -- Watchdog Timer Postscaler Select bits (bitmask:0x0F)
WDTPS = 1 0x00 1:1.
WDTPS = 2 0x01 1:2.
WDTPS = 4 0x02 1:4.
WDTPS = 8 0x03 1:8.
WDTPS = 16 0x04 1:16.
WDTPS = 32 0x05 1:32.
WDTPS = 64 0x06 1:64.
WDTPS = 128 0x07 1:128.
WDTPS = 256 0x08 1:256.
WDTPS = 512 0x09 1:512.
WDTPS = 1024 0x0A 1:1024.
WDTPS = 2048 0x0B 1:2048.
WDTPS = 4096 0x0C 1:4096.
WDTPS = 8192 0x0D 1:8192.
WDTPS = 16384 0x0E 1:16384.
WDTPS = 32768 0x0F 1:32768.
CONFIG3L (address:0x00FFFC, mask:0x02, default:0x02)
RTCSOSC -- RTCC Reference Clock Select bit (bitmask:0x02)
RTCSOSC = INTOSCREF 0x00 RTCC uses INTOSC/INTRC as reference clock.
RTCSOSC = T1OSCREF 0x02 RTCC uses T1OSC/T1CKI as reference clock.
CONFIG3H (address:0x00FFFD, mask:0x01, default:0x01)
CCP2MX -- CCP2 MUX (bitmask:0x01)
CCP2MX = ALTERNATE 0x00 RE7 / RB3.
CCP2MX = DEFAULT 0x01 RC1.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:50 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.