All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size
ROM
size
EEPROM
size
Common
SFRs
Features Configuration Bits RAM map SFR map
PIC18LF26J53
CONFIG1L (address:0x00FFF8, mask:0x7F, default:0x7F)
WDTEN -- Watchdog Timer (bitmask:0x01)
WDTEN = OFF 0x00 Disabled - Controlled by SWDTEN bit.
WDTEN = ON 0x01 Enabled.
PLLDIV -- PLL Prescaler Selection (bitmask:0x0E)
PLLDIV = 12 0x00 Divide by 12 (48 MHz oscillator input).
PLLDIV = 10 0x02 Divide by 10 (40 MHz oscillator input).
PLLDIV = 6 0x04 Divide by 6 (24 MHz oscillator input).
PLLDIV = 5 0x06 Divide by 5 (20 MHz oscillator input).
PLLDIV = 4 0x08 Divide by 4 (16 MHz oscillator input).
PLLDIV = 3 0x0A Divide by 3 (12 MHz oscillator input).
PLLDIV = 2 0x0C Divide by 2 (8 MHz oscillator input).
PLLDIV = 1 0x0E No prescale (4 MHz oscillator input drives PLL directly).
CFGPLLEN -- PLL Enable Configuration Bit (bitmask:0x10)
CFGPLLEN = ON 0x00 PLL Enabled.
CFGPLLEN = OFF 0x10 PLL Disabled.
STVREN -- Stack Overflow/Underflow Reset (bitmask:0x20)
STVREN = OFF 0x00 Disabled.
STVREN = ON 0x20 Enabled.
XINST -- Extended Instruction Set (bitmask:0x40)
XINST = OFF 0x00 Disabled.
XINST = ON 0x40 Enabled.
CONFIG1H (address:0x00FFF9, mask:0x07, default:0x07)
CPUDIV -- CPU System Clock Postscaler (bitmask:0x03)
CPUDIV = OSC4_PLL6 0x00 CPU system clock divide by 6.
CPUDIV = OSC3_PLL3 0x01 CPU system clock divide by 3.
CPUDIV = OSC2_PLL2 0x02 CPU system clock divide by 2.
CPUDIV = OSC1 0x03 No CPU system clock divide.
CP0 -- Code Protect (bitmask:0x04)
CP0 = ON 0x00 Program memory is code-protected.
CP0 = OFF 0x04 Program memory is not code-protected.
CONFIG2L (address:0x00FFFA, mask:0xFF, default:0xFF)
OSC -- Oscillator (bitmask:0x07)
OSC = INTOSC 0x00 INTOSC.
OSC = INTOSCO 0x01 INTOSCO (CLKO-RA6).
OSC = INTOSCPLL 0x02 INTOSCPLL.
OSC = INTOSCPLLO 0x03 INTOSCPLLO (CLKO-RA6).
OSC = HS 0x04 HS, USB-HS.
OSC = HSPLL 0x05 HS+PLL, USB-HS+PLL.
OSC = EC 0x06 EC (CLKO-RA6), USB-EC.
OSC = ECPLL 0x07 EC+PLL (CLKO-RA6), USB-EC+PLL.
SOSCSEL -- T1OSC/SOSC Power Selection Bits (bitmask:0x18)
SOSCSEL = RESERVED 0x00 Reserved.
SOSCSEL = LOW 0x08 Low Power T1OSC/SOSC circuit selected.
SOSCSEL = DIG 0x10 Digital (SCLKI) mode selected.
SOSCSEL = HIGH 0x18 High Power T1OSC/SOSC circuit selected.
CLKOEC -- EC Clock Out Enable Bit (bitmask:0x20)
CLKOEC = OFF 0x00 CLKO output disabled on the RA6 pin.
CLKOEC = ON 0x20 CLKO output enabled on the RA6 pin.
FCMEN -- Fail-Safe Clock Monitor (bitmask:0x40)
FCMEN = OFF 0x00 Disabled.
FCMEN = ON 0x40 Enabled.
IESO -- Internal External Oscillator Switch Over Mode (bitmask:0x80)
IESO = OFF 0x00 Disabled.
IESO = ON 0x80 Enabled.
CONFIG2H (address:0x00FFFB, mask:0x0F, default:0x0F)
WDTPS -- Watchdog Postscaler (bitmask:0x0F)
WDTPS = 1 0x00 1:1.
WDTPS = 2 0x01 1:2.
WDTPS = 4 0x02 1:4.
WDTPS = 8 0x03 1:8.
WDTPS = 16 0x04 1:16.
WDTPS = 32 0x05 1:32.
WDTPS = 64 0x06 1:64.
WDTPS = 128 0x07 1:128.
WDTPS = 256 0x08 1:256.
WDTPS = 512 0x09 1:512.
WDTPS = 1024 0x0A 1:1024.
WDTPS = 2048 0x0B 1:2048.
WDTPS = 4096 0x0C 1:4096.
WDTPS = 8192 0x0D 1:8192.
WDTPS = 16384 0x0E 1:16384.
WDTPS = 32768 0x0F 1:32768.
CONFIG3L (address:0x00FFFC, mask:0xFF, default:0xFF)
DSWDTOSC -- DSWDT Clock Select (bitmask:0x01)
DSWDTOSC = T1OSCREF 0x00 DSWDT uses T1OSC/T1CKI.
DSWDTOSC = INTOSCREF 0x01 DSWDT uses INTRC.
RTCOSC -- RTCC Clock Select (bitmask:0x02)
RTCOSC = INTOSCREF 0x00 RTCC uses INTRC.
RTCOSC = T1OSCREF 0x02 RTCC uses T1OSC/T1CKI.
DSBOREN -- Deep Sleep BOR (bitmask:0x04)
DSBOREN = OFF 0x00 Disabled.
DSBOREN = ON 0x04 Enabled.
DSWDTEN -- Deep Sleep Watchdog Timer (bitmask:0x08)
DSWDTEN = OFF 0x00 Disabled.
DSWDTEN = ON 0x08 Enabled.
DSWDTPS -- Deep Sleep Watchdog Postscaler (bitmask:0xF0)
DSWDTPS = 2 0x00 1:2 (2.1 ms).
DSWDTPS = 8 0x10 1:8 (8.3 ms).
DSWDTPS = 32 0x20 1:32 (33 ms).
DSWDTPS = 128 0x30 1:128 (132 ms).
DSWDTPS = 512 0x40 1:512 (528 ms).
DSWDTPS = 2048 0x50 1:2,048 (2.1 seconds).
DSWDTPS = 8192 0x60 1:8,192 (8.5 seconds).
DSWDTPS = K32 0x70 1:32,768 (34 seconds).
DSWDTPS = K131 0x80 1:131,072 (135 seconds).
DSWDTPS = K524 0x90 1:524,288 (9 minutes).
DSWDTPS = M2 0xA0 1:2,097,152 (36 minutes).
DSWDTPS = M8 0xB0 1:8,388,608 (2.4 hours).
DSWDTPS = M33 0xC0 1:33,554,432 (9.6 hours).
DSWDTPS = M134 0xD0 1:134,217,728 (38.5 hours).
DSWDTPS = M536 0xE0 1:536,870,912 (6.4 days).
DSWDTPS = G2 0xF0 1:2,147,483,648 (25.7 days).
CONFIG3H (address:0x00FFFD, mask:0x0B, default:0x0B)
IOL1WAY -- IOLOCK One-Way Set Enable bit (bitmask:0x01)
IOL1WAY = OFF 0x00 The IOLOCK bit (PPSCON<0>) can be set and cleared as needed.
IOL1WAY = ON 0x01 The IOLOCK bit (PPSCON<0>) can be set once.
ADCSEL -- ADC 10 or 12 Bit Select (bitmask:0x02)
ADCSEL = BIT12 0x00 12 - Bit ADC Enabled.
ADCSEL = BIT10 0x02 10 - Bit ADC Enabled.
MSSP7B_EN -- MSSP address masking (bitmask:0x08)
MSSP7B_EN = MSK5 0x00 5 Bit address masking mode.
MSSP7B_EN = MSK7 0x08 7 Bit address masking mode.
CONFIG4L (address:0x00FFFE, mask:0xBF, default:0xBF)
WPFP -- Write/Erase Protect Page Start/End Location (bitmask:0x3F)
WPFP = PAGE_0 0x00 Write Protect Program Flash Page 0.
WPFP = PAGE_1 0x01 Write Protect Program Flash Page 1.
WPFP = PAGE_2 0x02 Write Protect Program Flash Page 2.
WPFP = PAGE_3 0x03 Write Protect Program Flash Page 3.
WPFP = PAGE_4 0x04 Write Protect Program Flash Page 4.
WPFP = PAGE_5 0x05 Write Protect Program Flash Page 5.
WPFP = PAGE_6 0x06 Write Protect Program Flash Page 6.
WPFP = PAGE_7 0x07 Write Protect Program Flash Page 7.
WPFP = PAGE_8 0x08 Write Protect Program Flash Page 8.
WPFP = PAGE_9 0x09 Write Protect Program Flash Page 9.
WPFP = PAGE_10 0x0A Write Protect Program Flash Page 10.
WPFP = PAGE_11 0x0B Write Protect Program Flash Page 11.
WPFP = PAGE_12 0x0C Write Protect Program Flash Page 12.
WPFP = PAGE_13 0x0D Write Protect Program Flash Page 13.
WPFP = PAGE_14 0x0E Write Protect Program Flash Page 14.
WPFP = PAGE_15 0x0F Write Protect Program Flash Page 15.
WPFP = PAGE_16 0x10 Write Protect Program Flash Page 16.
WPFP = PAGE_17 0x11 Write Protect Program Flash Page 17.
WPFP = PAGE_18 0x12 Write Protect Program Flash Page 18.
WPFP = PAGE_19 0x13 Write Protect Program Flash Page 19.
WPFP = PAGE_20 0x14 Write Protect Program Flash Page 20.
WPFP = PAGE_21 0x15 Write Protect Program Flash Page 21.
WPFP = PAGE_22 0x16 Write Protect Program Flash Page 22.
WPFP = PAGE_23 0x17 Write Protect Program Flash Page 23.
WPFP = PAGE_24 0x18 Write Protect Program Flash Page 24.
WPFP = PAGE_25 0x19 Write Protect Program Flash Page 25.
WPFP = PAGE_26 0x1A Write Protect Program Flash Page 26.
WPFP = PAGE_27 0x1B Write Protect Program Flash Page 27.
WPFP = PAGE_28 0x1C Write Protect Program Flash Page 28.
WPFP = PAGE_29 0x1D Write Protect Program Flash Page 29.
WPFP = PAGE_30 0x1E Write Protect Program Flash Page 30.
WPFP = PAGE_31 0x1F Write Protect Program Flash Page 31.
WPFP = PAGE_32 0x20 Write Protect Program Flash Page 32.
WPFP = PAGE_33 0x21 Write Protect Program Flash Page 33.
WPFP = PAGE_34 0x22 Write Protect Program Flash Page 34.
WPFP = PAGE_35 0x23 Write Protect Program Flash Page 35.
WPFP = PAGE_36 0x24 Write Protect Program Flash Page 36.
WPFP = PAGE_37 0x25 Write Protect Program Flash Page 37.
WPFP = PAGE_38 0x26 Write Protect Program Flash Page 38.
WPFP = PAGE_39 0x27 Write Protect Program Flash Page 39.
WPFP = PAGE_40 0x28 Write Protect Program Flash Page 40.
WPFP = PAGE_41 0x29 Write Protect Program Flash Page 41.
WPFP = PAGE_42 0x2A Write Protect Program Flash Page 42.
WPFP = PAGE_43 0x2B Write Protect Program Flash Page 43.
WPFP = PAGE_44 0x2C Write Protect Program Flash Page 44.
WPFP = PAGE_45 0x2D Write Protect Program Flash Page 45.
WPFP = PAGE_46 0x2E Write Protect Program Flash Page 46.
WPFP = PAGE_47 0x2F Write Protect Program Flash Page 47.
WPFP = PAGE_48 0x30 Write Protect Program Flash Page 48.
WPFP = PAGE_49 0x31 Write Protect Program Flash Page 49.
WPFP = PAGE_50 0x32 Write Protect Program Flash Page 50.
WPFP = PAGE_51 0x33 Write Protect Program Flash Page 51.
WPFP = PAGE_52 0x34 Write Protect Program Flash Page 52.
WPFP = PAGE_53 0x35 Write Protect Program Flash Page 53.
WPFP = PAGE_54 0x36 Write Protect Program Flash Page 54.
WPFP = PAGE_55 0x37 Write Protect Program Flash Page 55.
WPFP = PAGE_56 0x38 Write Protect Program Flash Page 56.
WPFP = PAGE_57 0x39 Write Protect Program Flash Page 57.
WPFP = PAGE_58 0x3A Write Protect Program Flash Page 58.
WPFP = PAGE_59 0x3B Write Protect Program Flash Page 59.
WPFP = PAGE_60 0x3C Write Protect Program Flash Page 60.
WPFP = PAGE_61 0x3D Write Protect Program Flash Page 61.
WPFP = PAGE_62 0x3E Write Protect Program Flash Page 62.
WPFP = PAGE_63 0x3F Write Protect Program Flash Page 63.
WPCFG -- Write/Erase Protect Configuration Region (bitmask:0x80)
WPCFG = ON 0x00 Configuration Words page erase/write-protected.
WPCFG = OFF 0x80 Configuration Words page not erase/write-protected.
CONFIG4H (address:0x00FFFF, mask:0x0B, default:0x0B)
WPDIS -- Write Protect Disable bit (bitmask:0x01)
WPDIS = ON 0x00 WPFP<6:0>/WPEND region erase/write protected.
WPDIS = OFF 0x01 WPFP<6:0>/WPEND region ignored.
WPEND -- Write/Erase Protect Region Select bit (valid when WPDIS = 0) (bitmask:0x02)
WPEND = PAGE_0 0x00 Pages 0 through WPFP<6:0> erase/write protected.
WPEND = PAGE_WPFP 0x02 Pages WPFP<6:0> through Configuration Words erase/write protected.
LS48MHZ -- Low Speed USB mode with 48 MHz system clock bit (bitmask:0x08)
LS48MHZ = SYS24X4 0x00 System clock at 24 MHz USB CLKEN divide-by is set to 4.
LS48MHZ = SYS48X8 0x08 System clock at 48 MHz USB CLKEN divide-by is set to 8.

This page generated automatically by the device-help.pl program (2017-05-13 09:29:51 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.