| PIC12F529T48A | ||||
|---|---|---|---|---|
| CONFIG (address:0x0FFF, mask:0x07FF, default:0x05FF) | ||||
| OSC -- Oscillator (bitmask:0x0003) | ||||
| OSC = LP | 0x0FFC | LP Osc With 18 ms DRT. | ||
| OSC = XT | 0x0FFD | XT Osc With 18 ms DRT. | ||
| OSC = INTRC | 0x0FFE | INTRC With 1 ms DRT. | ||
| OSC = EXTRC | 0x0FFF | EXTRC With 1 ms DRT. | ||
| WDT -- Watchdog Timer Enable (bitmask:0x0004) | ||||
| WDT = OFF | 0x0FFB | Disabled. | ||
| WDT = ON | 0x0FFF | Enabled. | ||
| PARITY -- Configuration Word Parity (bitmask:0x0008) | ||||
| PARITY = CLEAR | 0x0FF7 | Parity bit clear. | ||
| PARITY = SET | 0x0FFF | Parity bit set. | ||
| MCLRE -- Master Clear Enable (bitmask:0x0010) | ||||
| MCLRE = OFF | 0x0FEF | RB3/MCLR Functions as RB3. | ||
| MCLRE = ON | 0x0FFF | RB3/MCLR Functions as MCLR. | ||
| IOSCFS -- Internal Oscillator Frequency Select (bitmask:0x0020) | ||||
| IOSCFS = 4MHz | 0x0FDF | 4 MHz INTOSC Speed. | ||
| IOSCFS = 8MHz | 0x0FFF | 8 MHz INTOSC Speed. | ||
| CPDF -- Code Protection bit - Flash Data Memory (bitmask:0x0040) | ||||
| CPDF = ON | 0x0FBF | Code protection on. | ||
| CPDF = OFF | 0x0FFF | Code protection off. | ||
| CP -- Code Protect State (bitmask:0x0780) | ||||
| CP = ENABLE | 0x097F | Code Protect Enabled. | ||
| CP = DISABLE | 0x0DFF | Disabled. | ||
This page generated automatically by the device-help.pl program (2017-05-13 09:29:46 UTC) from the 8bit_device.info file (rev: 1.36) of mpasmx and from the gputils source package (rev: svn 1308). The mpasmx is included in the MPLAB X.